Field effect transistor and method of manufacturing a field...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Reexamination Certificate

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07615430

ABSTRACT:
The invention relates to a method of manufacturing a field effect transistor, in which a semiconductor body of silicon is provided at a surface thereof with a source region and a drain region of a first conductivity type, which regions are both provided with extensions, and with a gate region situated above the channel region. A pn-junction is formed between the extensions and a neighboring part of the channel region using an amorphizing implantation followed by two implantations of dopants of opposite conductivity type, before the gate region is formed and at an angle with the surface of the semiconductor body which is substantially equal to 90 degrees. A steep and abrupt vertical part of the pn-junction is thus formed with a very low leakage current due to the absence of implantations defects. In some embodiments, a low temperature anneal is used to regrow crystalline silicon.

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patent: 6180476 (2001-01-01), Yu
patent: 6245618 (2001-06-01), An et al.
patent: 6268640 (2001-07-01), Park et al.
patent: 6521502 (2003-02-01), Yu
patent: 2001/0014495 (2001-08-01), Yu
patent: 2002/0102801 (2002-08-01), Lai et al.
patent: 2003/0207527 (2003-11-01), Mehrad et al.

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