Field effect transistor and method of fabrication

Details Field effect transistor and method of fabrication Field effect transistor and method of fabrication

2002-01-31

2003-06-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S359000

Reexamination Certificate

active

06579768

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to field effect transistors, and more particularly, to the shape of the channel region of a field effect transistor and a method of controlling the shape.
BACKGROUND OF THE INVENTION
The Insulated Gate Field Effect Transistor (IGFET) has become the workhorse of the semiconductor industry. Integrated circuits containing tens of millions of such IGFETs are routinely fabricated. In the design of such integrated circuits, it is necessary to know the characteristics of transistors with various widths and lengths of the channel region. IGFETs with very wide channel regions are typically used when relatively large currents are needed, such as driver transistors used to transmit signals to other devices exterior to the integrated circuit. Narrow channel IGFETS are typically used to transmit signals to a few, closely located transistors within an integrated circuit.
In the design of such integrated circuits it is important that the electrical characteristics of IGFETs with different channel sizes be known, and, if the electrical characteristics, such as threshold voltage, current drive capability, and sub-threshold leakage, are not identical, that the characteristics of transistors with different shape factors at least be quantifiable.
One of the effects which leads to transistors of different channel width having different characteristics is that the transistor characteristic at the edge of the channel may be different than the transistor characteristics at the center of a wide channel. If the channel of the transistor is very wide, the transistor characteristics will be dominated by the characteristics at the center of the channel. If the transistor is of a narrow width, the transistor characteristics may be dominated by the characteristics at the edge of the channel.
One parameter which can have a large influence on transistor characteristics is the magnitude of electric field in the gate insulator at the surface of the semiconductor. This electric field arises from the application of a potential to the gate electrode of the transistor relative to the body of the transistor. In the center of the channel region of a wide channel transistor this electric field is determined by the thickness and dielectric constant of the gate dielectric (insulator), and by the surface doping of the underlying semiconductor material. At the edge of the channel region, however, the shape of the edge of the semiconductor and the shape of the gate electrode, as well as the thickness of the gate dielectric, also influence the electric field at the surface of the semiconductor. In particular, if the edge of the semiconductor has a sharp corner with a small radius of curvature, the electric field for a given value of applied gate potential will be higher at this edge than in the central region of the channel. This can affect the characteristics of the IGFET in several ways.
The higher electric field at the edge of the channel region for a given gate potential can result in a premature turn-on of the IGFET, i.e., current will flow at the edge of the IGFET before current flow begins in the central portion of the IGFET. In effect, the threshold voltage at the edge of the IGFET is lower than that at the center thereof, and the effective threshold voltage of an IGFET is a function of the width of the channel. Deleterious circuit effects can occur when a potential is applied to the gate of a narrow channel IGFET which is of a magnitude sufficient to stop current flow in a wide channel IGFET, but which may be such as to allow significant current flow to take place in a narrow channel IGFET. Such an effect would manifest itself as an apparent increased sub-threshold leakage current in the narrow channel IGFETs used in the circuit.
Physically deleterious effects may also occur if the increase of electric field in the gate insulator at the edge of the channel of the IGFET, for a given applied gate potential, is excessive, and results in the electric field exceeding the maximum allowable electric field to prevent breakdown of the gate insulator material. Such excessive electric field in the gate insulator material may result in reduced reliability of the transistors.
FIG. 1
shows a sectional view of a channel region of a prior art IGFET fabricated in a Shallow Trench Isolation (STI) technology. A silicon island
14
, having a channel portion
14
b
, is formed in a semiconductor body
12
, which is typically silicon. Channel portion
14
b
has a top surface
14
bb
. Surrounding the island
14
is an insulating region
16
that has a lower surface
16
b
in contact with portions of the silicon body
12
, and has side walls
16
c
in contact with side walls
14
bbb
of island
14
. A top surface
16
a
of insulating region
16
is at a level above the top surface
14
bb
of channel region
14
b
. Insulating region
16
has been formed using Shallow Trench Isolation (STI) techniques. A gate insulator layer
18
(dielectric layer) having an upper surface
18
a
is on the upper surface
14
bb
of the channel region
14
b
. A gate region
20
lies on the upper surfaces
18
a
and
16
a
of the insulating regions
18
and
16
, respectively. Gate region
20
overlies and typically extends beyond channel region
14
b
. The gate region
20
is typically doped polysilicon, but can be a material of greater conductivity, such as aluminum, or a metal silicide, such as tungsten silicide, or a composite layer composed of a metal silicide layer and a layer of polysilicon. The corners
30
of the channel region
14
b
, defined by the intersection of side walls
14
bbb
and top surface
14
bb
, are shown as right angles, with little or no radius of curvature. The sharp corners
30
are characteristic of transistors fabricated using prior art techniques, and lead to higher electric fields in the gate insulator
18
in the vicinity of the sharp corners
30
than in the center
31
of the channel region. Such a transistor will suffer from the deleterious effects described above.
It has been found in the prior art that the radius of the corners
30
may be increased, and the electric fields in the gate insulator
18
in the vicinity of the sharp corners
30
reduced, by increasing the thickness of various sacrificial oxide layers used in the fabrication of the prior art structure shown in FIG.
1
. The use of such thicker oxide layers will require an increased “time at temperature” during the fabrication of the structure, which results in undesirable dopant diffusion. Thus, one achieves the reduction of one deleterious effect, high electric fields in the gate insulator, but at the price of another deleterious effect, increased dopant diffusion.
Other prior art attempts to increase the radius of the corners
30
result in the top surface
14
bb
of the channel region
14
b
being non-planar. This can lead to undesirable physical or electrical characteristics of the transistors formed. Still other prior art attempts to increase the radius of the corners
30
result in the formation of shallow trenches in the STI insulating region
16
adjacent to the side walls
14
bbb
of the silicon island
14
. This can lead to undesirable electrical characteristics of the transistors formed, or difficulties in later processing steps.
It is desirable to fabricate the IGFETs in such a manner that as few as possible deleterious effects take place at the edges of the channels thereof, and throughout the complete IGFET structure.
SUMMARY OF THE INVENTION
The present invention is directed to an Insulated Gate Field Effect Transistor (IGFET) in which a region of a semiconductor channel region of the IGFET is shaped so as to reduce the electric field in the gate insulator resulting from a given applied gate potential, and to a method for fabricating an IGFET so as to result in the elimination of sharp corners of semiconductor at the edge of the channel region of the IGFET.
Viewed from a first process aspect, the present invention is directed to a method for forming a curved edge on a semiconductor island. The method

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