Field effect transistor and method of fabricating the same

Details Field effect transistor and method of fabricating the same Field effect transistor and method of fabricating the same

2006-06-13

2006-06-13

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S307000, C257S336000, C257S344000, C257S408000

Reexamination Certificate

active

07060580

ABSTRACT:
Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

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patent: 2004/0056304 (2004-03-01), Ahmed et al.
Yang-Kyu Choi, et al.; “A Spacer Patterning Technology for Nanoscale CMOS”; IEEE Transaction on Electron Devices, vol. 49, No. 3, Mar. 2002; pp. 436-441.
A. Chatterjee, et al.; Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process; IEDM 97; pp. 821-824.

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