FET read only memory cell with word line augmented precharging o

Details FET read only memory cell with word line augmented precharging o FET read only memory cell with word line augmented precharging o

1983-09-20

1988-02-16

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365104, G11C 1700

Patent

active

047259868

ABSTRACT:
An FET read only memory cell circuit is disclosed wherein word lines serve to augment the precharging of the bit lines. If an FET read only memory site is preprogrammed as a binary one, for example, then when its word line is pulsed, the bit line will be insured to have an affirmatively high potential, representing a binary one state. This improves the reliability of the operation of the circuit by minimizing the effects of charge leakage from the bit line.

REFERENCES:
patent: 3866186 (1975-02-01), Suzuki
patent: 4006469 (1977-01-01), Leehan et al.
patent: 4151603 (1979-04-01), Gladstein
patent: 4208727 (1980-06-01), Redwine et al.
patent: 4240151 (1980-12-01), Kawagoe
patent: 4262341 (1981-04-01), Mogi et al.
patent: 4375600 (1983-03-01), Wu
patent: 4389705 (1983-06-01), Sheppard
patent: 4413330 (1983-11-01), Chao et al.
IBM Technical Disclosure Bulletin-vol. 15, No. 8, Jan. 1973, pp. 2371-2372.
IBM Technical Disclosure Bulletin-vol. 16, No. 5, Oct. 1973, p. 1642.
IBM Technical Disclosure Bulletin-vol. 25, No. 3A, Aug. 1982, pp. 1070-1072.

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