Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-11-16
2001-08-14
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S145000, C365S189090, C365S149000, C365S194000, C365S195000, C365S226000, C327S534000, C327S535000, C327S537000, C327S530000
Reexamination Certificate
active
06275425
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to non-volatile ferroelectric memories. More particularly, the present invention relates to voltage boosting circuitry that enables extremely low voltage operation of non-volatile ferroelectric memories.
Non-volatile memories based on ferroelectric materials are becoming increasingly popular due to their advantages over floating-gate non-volatile memory technologies. The primary advantages of ferroelectric nonvolatile memories are low write voltage (less than five volts versus greater than ten volts for competing technologies), fast write time (less than 100 ns versus volts for competing technologies), fast write time (less than 100 ns versus greater than 1 ms) and low power consumption (charge-based read/write versus current-based read/write). Historically, ferroelectric materials have been developed for integrated circuits energized with a five volt power supply. volts for competing technologies), fast write time (less than 100 ns versus In recent years, a large migration has occurred to 3.3 volt system power supplies. While ferroelectric memory manufacturers have worked to develop production worthy three volt materials, more and more designs are now migrating to 1.8 volt supplies and even lower voltage supplies. Current designs using available ferroelectric materials and conventional ferroelectric memory architectures are inoperable using these 1.8 volt systems because there is simply not enough voltage to generate practically detectable amounts of switched charge.
What is desired, therefore, is a circuit design and architecture for a ferroelectric memory that enables reliable low voltage power supply operation (such as 1.8 volt power supply operation) using state-of-the-art 3.3 volt and other higher-voltage compatible ferroelectric materials.
SUMMARY OF THE INVENTION
It is, therefore, a principal object of the present invention to improve low voltage power supply operation in a ferroelectric memory.
It is another object of the invention to allow ferroelectric materials developed for use with 3.3 volt and five volt power supplies to be used at lower voltages such as 1.8 volts.
It is an advantage of the invention that the CMOS implementation of the present invention allows for uninhibited operation to 2.7 volts and below, even with integrated circuit processes designed for five volt operation. The basic circuitry of the present invention can be expanded if desired to provide real-time variation in boosted voltage levels, which may become important in wide voltage range designs. One-shot boosting as taught in the present invention draws significantly less current than a free-running charge pump and is immediately available upon power-up. When combined with level-translating decoders, a global or local boosted voltage is generated and routed throughout the memory employing significant die area savings and improved control of the boosted voltage level.
According to the present invention, the disclosed circuits enable 1.8 volt designs to be implemented using the state-of-the-art generation of three-volt ferroelectric films. Furthermore, they offer an alternative to conventional word-line boosting circuits, which cease to operate when the power supply voltage falls below approximately two times a body-effected N-channel threshold voltage. The disclosed boost circuits operate well at low voltages and can take advantage of the high dielectric constant of ferroelectric materials to reduce circuit area.
In the ferroelectric memory circuit, the node requiring voltage boosting is tied to the system supply through a PMOS transistor until voltage boosting is required. The rising edge of a boost control signal disconnects the node to be boosted from the power supply, and the node is capacitively boosted using ferroelectric capacitors. In one embodiment, the level of boost is controlled by selecting the number and size of the boost capacitors. The voltage boost circuit is used to generate a global or local boosted voltage level. In another embodiment, a charge pool method of boosted voltage sharing is used.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.
REFERENCES:
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patent: 5854568 (1998-12-01), Moscaluk
patent: 5896042 (1999-04-01), Nishimura et al.
patent: 5999461 (1999-12-01), Verhaeghe et al.
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patent: 6141237 (2000-10-01), Eliason et al.
Hogan & Hartson LLP.
Meza, Esq. Peter J.
Ramtron International Corporation
Tran Andrew Q.
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