Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-01-08
2003-11-11
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S201000, C365S210130
Reexamination Certificate
active
06646905
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a storage device having an array of ferroelectric memory cells each containing information storing ferroelectric capacitors having a ferroelectric film as an insulator.
BACKGROUND OF THE INVENTION
Ferroelectric materials have a characteristic that, once an electric polarization is created by an applied electric field, it remains even after the electric field is removed. Therefore, the polarization in a ferroelectric material will not be erased unless an opposite electric field of a certain intensity is applied to the material. Hence, it exhibits a hysteresis characteristic.
A ferroelectric memory, which utilizes ferroelectric capacitors for storing information and contains a ferroelectric film as an insulator, is a fast rewritable non-volatile memory, taking advantage of the ferroelectric property that it has a prolonged residual polarization and that it has a fast reversible speed (reversible within a few ns).
In addition, unlike EEPROM and flash memory which require a high voltage (about 10-12 Volts) in writing and reading data, a ferroelectric memory has a low reversion voltage (in the range of about 3-5 Volts). Hence, the ferroelectric memory can be operated by a low voltage power source.
FIG. 1
illustrates a ferroelectric storage device having a ferroelectric memory. This memory has a cell structure consisting of 2 transistors and 2 capacitors. (Such structure will be hereinafter referred to as 2Tr-2C cell structure). As shown in
FIG. 1
, the ferroelectric storage device includes: selection transistors Q
00
-Q
11
; ferroelectric capacitors C
00
-C
11
for storing information; word lines WL
0
and WL
1
connected to the respective gates of the transistors Q
00
-Q
11
; bit lines BL
0
and BL
1
; plate lines PL
0
and PL
1
; and bit line capacitors Cbl representing parasitic capacitances of the bit lines BL
0
and BL
1
. The selection transistor Q
00
, ferroelectric capacitor C
00
, selection transistor Q
01
, and ferroelectric capacitor C
01
constitutes a memory cell MC
0
. A memory cell MC
1
also has a similar structure. A memory array comprises a multiplicity of such memory cells. The storage device of
FIG. 1
also includes a bit selection circuit
1
and a voltage detection means (sense amplifier, SA) for detecting a potential difference between two bit lines BL
0
and BL
1
.
Data write and data read to such a ferroelectric memory cell as memory cell MC
0
in a ferroelectric storage device are performed as follows. The same operation will be performed to other ferroelectric memory cells.
In a data write operation, the word line WL
0
is raised to a high potential (HIGH) to turn on the selection transistors Q
00
and Q
01
. At the same time the bit line BL
0
is raised to HIGH, and the bit line BL
1
to a low potential (LOW) by the bit selection circuit
1
. Under this condition, the plate line PL
0
is first pulled to LOW and then to HIGH and back to LOW again.
Through a sequential change in potential LOW-HIGH-LOW of the plate line PL
0
, the ferroelectric capacitor C
00
coupled with the bit line BL
0
is positively polarized, while the ferroelectric capacitor C
01
coupled with the bit line BL
1
is negatively polarized. This condition of the capacitors represents data “1”. To write data “0”, opposite potentials are given to the bit lines BL
0
and BL
1
.
In a read operation, the plate line PL
0
is initially set to LOW, and the bit lines BL
0
and BL
1
are set to LOW by the bit selection circuit
1
to precharge or bring the bit lines to 0 Volt. The bit lines BL
0
and BL
1
are then floated by a signal from the bit selection circuit
1
. The word line WL
0
is set to HIGH to turn ON the selection transistors Q
00
and Q
01
. Under this condition, the ferroelectric capacitor C
00
and the bit line capacitor Cbl coupled with the bit line BL
0
are connected in series, while the ferroelectric capacitor C
01
and the bit line capacitor Cbl coupled with the bit line BL
1
are connected in series.
Next, the plate line PL
0
is pulled HIGH, so that the bit lines BL
0
and BL
1
acquire respective potentials determined by the electrostatic capacitances of the ferroelectric capacitors C
00
, C
01
and the bit line capacitor Cbl. Then the polarization of the ferroelectric capacitor C
00
coupled with the bit line BL
0
is reversed if the data stored in the memory is “1”, thereby generating a relatively high potential on the bit line BL
0
. On the other hand, the polarization of the ferroelectric capacitor C
01
coupled with the bit line BL
1
will not be reversed, yielding a relatively low potential on the bit line BL
1
.
The potential difference between the two bit lines BL
0
and BL
1
is detected by the sense amplifier SA, thereby distinguishing between “0” and “1” as follows:
Read data is recognized as “1” if the potential difference (BL
0
−BL
1
)>0.
Read data is recognized as “0” if the potential difference (BL
0
−BL
1
)<0.
Since data read from a memory that utilizes ferroelectric capacitors destroys the data stored in the memory, each of the bit lines BL
0
and BL
1
is set to HIGH or LOW, depending on the data stored, to restore the data in the memory. For example, the bit lines BL
0
and BL
1
are set to HIGH and LOW, respectively, when the data is “1”.
So far 2Tr-2C cell structure of a ferroelectric storage device has been discussed. A ferroelectric storage device utilizing one transistor and one capacitor (referred to as 1Tr-1C structure) is also known. Such 1Tr-1C cell structure ferroelectric storage device is provided with a reference voltage generation means for providing a reference voltage to detect the difference in voltage generated on two bit lines at the time of data read. Data read operation for the 1Tr-1C cell structure device is essentially the same as for 2Tr-2C cell structure device.
Since in the ferroelectric storage device that uses a memory array of ferroelectric capacitors the content of a memory cell is determined by the potential difference between two bit lines, it is necessary that a voltage margin is secured for data read.
Conventionally, tests are performed on a ferroelectric storage device during manufacturing and a test period by screening each memory cell before and/or after it is packaged. In the tests a memory is determined to be defective or not by checking if data “0” and “1” can be correctly written to and read from the memory. However, such conventional tests cannot assess operational margin of the storage device that has passed the tests, so that the test cannot verify if the memory has a desired operational margin as designed or not.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to provide a reliable ferroelectric storage device having an array of ferroelectric memory cells, by measuring bit line voltages that arises from the electric charges remaining in the ferroelectric memory cells, thereby quantitatively assessing deviations in characteristics and degree of defect/degradation of the ferroelectric capacitors in the cells.
In accordance with one aspect of the invention, there is provided a ferroelectric storage device having 2Tr-2C cell structure, comprising:
memory cells each including
a first ferroelectric capacitor C
0
connected in series with a first selection transistor Q
0
which is selected by a word line WL; and
a second ferroelectric capacitor C
1
connected in series with a second selection transistor Q
1
which is selected by the word line, the first and second ferroelectric capacitors having opposite polarization;
a first bit line BL
0
connected to one end of the series connection of the first ferroelectric capacitor C
0
and the first selection transistor Q
0
and having a bit line capacitor Cbl;
a second bit line BL
1
connected to one end of the series connection of the second ferroelectric capacitor C
1
and the second selection transistor Q
1
, and having a bit line capacitor Cbl;
a plate line PL connected to the other end of the series connection of the first ferroelectric capacitor C
0
and the first selection tran
Dinh Son T.
Hogan & Hartson
Rohm & Co., Ltd.
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