Ferroelectric random access memory device and fabrication...

Details Ferroelectric random access memory device and fabrication... Ferroelectric random access memory device and fabrication...

1998-11-24

2001-05-08

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S310000

Reexamination Certificate

active

06229166

ABSTRACT:

This application claims priority under 35 U.S.C. §119 to Korean Application No. 97-82093, which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabrication method therefor, and more particularly, to a ferroelectric random access memory (FRAM) device and a fabrication method therefor.
2. Description of the Related Art
A ferroelectric material has a ferroelectricity. The ferroelectricity is a physical property in which if an external voltage is applied to electric dipoles arranged in the ferroelectric material, a spontaneous polarization of the electric dipoles is generated. A remnant polarization of some constant level remains even after the external electric field is removed. When the remnant polarization of the ferroelectric material is used for storing data, the data can be stored without an external voltage. Also, application of a reverse external field causes polarization in the opposite direction.
The FRAMs using the ferroelectric material are largely classified into two types; a first type which operates by detecting a change in a charge amount stored in a ferroelectric capacitor, and a second type which operates by detecting a change in resistance of a semiconductor due to spontaneous polarization of the ferroelectric material. The first type is typically adapted to a structure in which a unit cell is constituted by one capacitor and one transistor. Particularly, this first type is widely applied to a DRAM, such that a thick interlayer insulating layer is formed on a CMOS structure and a ferroelectric capacitor is formed thereon.
The second type is typically adapted to a metal ferroelectric metal insulator semiconductor (MFMIS) field effect transistor (FET) structure. In the MFMIS FET structure, a unit cell is constituted by one transistor.
The structures of both types have a ferroelectric capacitor structure formed by depositing a lower metal layer/a ferrorelectric layer/an upper metal layer. The most widely used ferroelectric capacitor is a ferroelectric layer using PZT (Pb(Zr
x
Ti
1−x
) O
3
). The PZT (Pb(Zr
x
Ti
1−x
) O
3
) is used because its Curie temperature is relatively high, i.e., 230~490° C., it has different crystalline phases according to Zr/Ti composition and temperature, and it has a high dielectric constant.
However, in the conventional capacitor having a structure of a lower metal layer-PZT layer-upper metal layer, an imprint phenomenon in which a hysteresis curve moves toward a positive or a negative direction along an electric field axis occurs. If the imprint phenomenon occurs, the absolute values of positive and negative coercive voltages become different from each other, which destroys symmetry and reduces a remnant polarization value Pr.
The imprint phenomenon is caused by a difference in characteristics between an upper interface between the upper metal layer and PZT layer and a lower interface between the lower metal layer and PZT layer. This difference in characteristics is caused by a thermal treatment of the PZT layer. In other words, after the PZT layer is deposited on the lower metal layer, if the PZT layer is thermally treated for crystallization, Pb present in the PZT layer moves toward the interface adjacent the lower metal layer, thereby changing the interface characteristics. However, since the upper metal layer is formed on the thermally treated PZT layer, the upper layer does not experience such a change as the lower metal layer. Thus, the upper and lower interfaces of the PZT layer become different in their characteristics, causing the imprint phenomenon.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a ferroelectric random access memory (FRAM) device having a ferroelectric layer with the same characteristics of upper and lower interfaces so that an imprint phenomenon does not occur.
It is another object of the present invention to provide a fabrication method suitable for fabricating, a FRAM device having, a ferroelectric layer with the same upper and lower interface characteristics.
Accordingly, the first and other objects may be realized by providing a ferroelectric random access memory (FRAM) device including a lower electrode, a lower seed layer formed on the lower electrode, a ferroelectric layer formed on the lower seed layer, an upper seed layer formed on the ferroelectric layer, and an upper electrode formed on the upper seed layer. The upper and lower seed layers make characteristics of an upper interface and a lower interface of the ferroelectric match each other. The ferroelectric layer may be a PZT layer.
The upper and lower seed layers may be composed of a material having a crystallization temperature lower than that of a material of the ferroelectric layer. The upper and lower seed layers may be composed of a ferroelectric material having a lattice constant similar to that of a material of the ferroelectric layer. The upper and lower seed layers may be composed of PbTiO
3
, TiO
2
or PZT having at least one of a higher Pb content and a higher Ti composition ratio than the PZT of the ferroelectric layer. The upper and lower seed layers are composed of the same material.
The upper and lower electrodes may include a Pt-group metal layer, a conductive oxide layer or a dual layer of the Pt-group metal layer and the conductive oxide layer. The upper and lower electrodes have the same structure. A switching element may be electrically connected to the lower electrode. The FRAM device may further include a gate insulating layer under the first electrode, a semiconductor substrate under the gate insulating layer, and source and drain regions in a portion of the semiconductor substrate adjacent to a periphery of the gate insulating layer.
The second and other objects of the present invention may be realized by providing a method for fabricating a ferroelectric random access memory (FRAM) device including forming a lower electrode, forming a lower seed layer on the lower electrode, forming a ferroelectric layer on the lower seed layer, forming an upper seed layer on the ferroelectric layer, annealing a resulting structure including the upper seed layer, including making characteristics of a lower face and an upper face of the ferroelectric layer be the same and completing a stable perovskite crystal structure of the ferroelectric layer, and forming an upper electrode on the upper seed layer.
The forming the ferroelectric layer may include forming a PZT ferroelectric layer on the lower seed layer. The forming the upper and lower seed layers may include using a material having a crystallization temperature lower than that of a material for forming the ferroelectric layer. The forming the upper and lower seed layers may include using a ferroelectric material having a lattice constant similar to that of a material for forming the ferroelectric layer. The upper and lower seed layers may include using PbTiO
3
, TiO
2
or PZT having at least one of a higher Pb content and a higher Ti composition ratio than a PZT to be used to form the ferroelectric layer.
The forming the lower electrode and the upper electrode may include using a Pt-group metal layer, a conductive oxide layer or a dual layer of the Pt-group metal layer and the conductive oxide layer. Prior to the forming the lower electrode, forming a switching element to be electrically connected to the lower electrode may be included. The method may further include, before the forming the lower electrode, providing a semiconductor substrate and forming a gate insulating layer on the semiconductor substrate, and, after the forming the upper electrode, forming source and drain regions in a portion of the semiconductor substrate adjacent to a periphery of the gate insulating layer.
According to the present invention, since the characteristics of the upper and lower interfaces become the same with each other by upper and lower seed layers, an imprint phenomenon can be effectively prevented i

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