Ferroelectric random access memory device

Details Ferroelectric random access memory device Ferroelectric random access memory device

2001-08-16

2003-01-07

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090

Reexamination Certificate

active

06504748

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-64055, filed on Oct. 30, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a semiconductor memory device and, more specifically, to a ferroelectric random access memory (RAM) device.
BACKGROUND OF THE INVENTION
Nonvolatile memory devices (NVMs) maintain stored data with applied power, as well as following removal of power. Such devices are realized by adopting a ferroelectric material, such as a PZT, having hysteresis characteristics.
Lead-zirconate-titanate, commonly referred to as PZT, is a well-known material used in integrated circuits. The use of PZT is disclosed in U.S. Pat. Nos. 5,028,455 and 4,946,719 issued to William D. Miller et al., and B. M. Melnick, et al., “Process Optimization and Characterization of Device Worthy Sol-Gel Based PZT for Ferroelectric Memories”, in Ferroelectrics, Vol 109, pp. 1-23 (1990).
Adoption of PZT in realizing memory cells of the NVMs enables the NVMs to be constructed in a simple structure. Ferroelectric random access memories (RAMs) having nonvolatile characteristics can be operated at high speed; thus, such ferroelectric RAM devices have been met with interest by memory chip producers.
In such devices, each ferroelectric memory cell is composed of a ferroelectric capacitor and a switching transistor, and stores a logic state of data (i.e., binary information “1” or “0”) according to the electric polarization state of the ferroelectric capacitor. When a voltage is loaded to both ends of the ferroelectric capacitor, the ferroelectric material is polarized. Depending on the direction of the electric field applied across the ferroelectric capacitor, the ferroelectric material can have two polarization directions. A first direction can be used to represent a data “1”, the other direction “0”. In this case, a switching voltage to cause the polarization is called as a coercive voltage. The data stored in the cell is sensed in response to a change in the amount of electric charge loaded into a bit line, by loading a difference voltage at both ends of the ferroelectric capacitor.
FIG. 1
is a circuit diagram for illustrating a memory cell MC composed of 1-transistor and 1-capacitor (1T/1C). The memory cell MC is composed of a switching transistor TR and a ferroelectric capacitor CF. That is, the memory cell MC is composed of 1-transistor and 1-capacitor for each bit of memory storage. The switching transistor TR has two main electrodes coupled to one end of the ferroelectric capacitor CF and a bit line BL, respectively, a drain, a source, and a gate coupled to a word line WL. Another end of the ferroelectric capacitor CF is coupled to a pale line PL.
Reading/writing operations of the memory call MC are illustrated with reference to FIG.
2
. As shown in
FIG. 2
, the ferroelectric capacitor CF exhibits hysteresis characteristics against a voltage across the both ends. Thus, 1 bit of data is stored to the ferroelectric capacitor CF as a difference of polarization P between polarization state points ‘a’ and ‘e’ when the applied voltage is zero (i.e., V=0). The 1 bit data of “1” and “0” correspond with the polarization state points ‘a’ and ‘e’, respectively. This relationship is described as follows.
Suppose that the ferroelectric capacitor CF at the polarization state point ‘a’ stores a data value “1”. When the switching transistor TR is turned on by loading a high voltage (i.e., power supply voltage Vcc) to the word line WL and a negative voltage −Ve is loaded to the ferroelectric capacitor CF through the bit line BL and the plate line PL (or, a pulse signal is loaded to the plate line PL), a polarization state P of the ferroelectric capacitor CF is changed from the polarization state point ‘a’ to a polarization state point ‘d’ via the polarization state points ‘b’ and ‘c’. The electric charge Q
1
corresponding to the state transition is transferred between the bit line BL and the ferroelectric capacitor CF through the switching transistor TR. The charge transfer is detected by a sense amplifier (not shown) coupled to the bit line BL, and the transfer means that the data “1” is read out from the memory cell MC. After reading out the data “1” from the memory cell MC, the data “1” on the bit line BL is written back to the memory cell MC by loading a pulse signal to the plate line PL. The writing result causes a reverse state transition from the polarization state point ‘e’ to a polarization state point ‘h’ via polarization state points ‘f’ and ‘g’.
However, as shown in
FIG. 2
, in case that the ferroelectric capacitor CF at the polarization state point ‘e’ stores a data “0”, a polarization state P of the ferroelectric capacitor CF is changed from the polarization state point ‘e’ to the polarization state point ‘d’ via the polarization state points ‘e’ and ‘c’, when the switching transistor TR is turned on by loading a high voltage (i.e., power supply voltage Vcc) to the word line WL and a negative voltage −Ve is loaded to the ferroelectric capacitor CF through the bit line BL and the plate line PL (or, a pulse signal is loaded to the plate line PL). The electric charge Q
0
corresponding to the state transition is transferred between the bit line BL and the ferroelectric capacitor CF through the switching transistor TR. The charge transfer is detected by a sense amplifier (not shown) coupled to the bit line BL, and the transfer means that the data “0” is read out from the memory cell MC.
In a ferroelectric RAM device, a memory cell array is provided as shown in FIG.
1
. The memory cells are arranged as a matrix format intersecting a plurality of rows and columns. Each of memory cells is coupled to a corresponding word line and a plate line. When a certain word line is selected to perform a read/write operation, as well known to a person skilled in the art, one end of the ferroelectric capacitor CF coupled to the plate line corresponding to respective unselected word lines, is floated during the read/write operation. Therefore, the voltage level between the both ends of the ferroelectric capacitor CF may be changed by adjacent signals. In other words, the floated plate lines may be boosted by adjacent signals. In this case, the polarization state of the ferroelectric capacitor CF coupled to the floated plate line is changed as much as the voltage variation between the both ends of the capacitor CF. Thus, it is possible that the data stored in the memory cell MC can be compromised.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a ferroelectric memory device for preventing the boosting of voltage in unselected plate lines by adjacent signals.
In order to attain the above objects, according to an aspect of the present invention, there is provided a nonvolatile memory device comprising: a first word line; a plurality of second word lines corresponding to the first word line; a plurality of plate lines corresponding to the respective second word lines; a plurality of memory cells coupled to the respective second word lines, wherein each of memory cells has a transistor for transferring electric charges and a ferroelectric capacitor; and a plate line driving circuit coupled to the plate lines, for transmitting a plate line drive signal to the plate lines when the first word line is selected, and for connecting the plate lines to the first word line when the first word line is unselected.
In a preferred embodiment, the plate line driving circuit comprises: a first switching element for transmitting the plate line drive signal to the plate lines in response to a signal on the first word line; and a second switching element for connecting the plate lines and the first word line, electrically, when the plate line drive signal is activated. The first and second switching elements preferably comprise transistors, for example N-type MOS transistors.
A third switching element is preferably coupled between a control electrode o

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