Ferroelectric memory with disturb protection

Details Ferroelectric memory with disturb protection Ferroelectric memory with disturb protection

1999-05-19

2000-11-21

Phan, Trong

Static information storage and retrieval

Systems using particular element

Ferroelectric

365148, G11C 1122, G11C 1100

Patent

active

061512419

ABSTRACT:
A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d >10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d <0.1.times.1/(2.pi.fC.sub.F).

REFERENCES:
patent: 4712876 (1987-12-01), Umeda et al.
patent: 5224069 (1993-06-01), Natori
patent: 5341325 (1994-08-01), Nakano et al.
patent: 5512773 (1996-04-01), Wolf et al.
patent: 5579258 (1996-11-01), Adachi
patent: 5699035 (1997-12-01), Ito et al.

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