Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-04-01
2003-03-25
Le, Vu A (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S063000, C365S149000
Reexamination Certificate
active
06538914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to ferroelectric memory, and more particularly to memory architecture that enables a ferroelectric memory cell with one transistor and one capacitor (“1T/1C”) in which the bit lines and plate lines are parallel. The invention also relates to an operating method for a ferroelectric memory device that reduces bit line noise caused by voltage pulses across a plate line.
2. Description of the Related Art
As the capacity and packing densities of semiconductor memory devices increase, capacitors take up larger portions of total area required for the memory cells of these devices. In order to shrink the size of memory cell capacitors and improve the overall packing density of memory cell devices, manufacturers have preferred a one-transistor one-capacitor (1T/1C) circuit with high density, but which must be continuously refreshed. These are referred to generally as dynamic random access memory (DRAM) devices. These circuits require refresh mechanisms to frequently restore the charged stored in each memory cell. Hence, these circuits are volatile in that memory loss will occur when power is removed such that refresh circuitry cannot operate. Static random access memory (SRAM) typically involves increasing complexity of the memory cell so that refresh mechanisms are not required. SRAM often has much faster access times than DRAM, but continues to suffer data loss when power is removed. SRAM circuits require more devices in each memory cell, and so are more expensive to produce.
Non-volatile memory is available in several forms. Conventional electrically programmable read only memory (EPROM), erasable electrically programmable read only memory (EEPROM) and flash EPROM devices store charge in the form of trapped charges in the memory cell's dielectric. The trapped charges are stable over a longer period of time, and so do not require dynamic refresh. However, the length of time that the stored charge is stable is limited. Moreover, conventional non-volatile memory tends to be slower to write, and requires significant power to write. Hence, conventional nonvolatile memory devices are not suitable replacements for volatile memory devices, and they tend to be used for a limited number of purposes.
Ferroelectric materials have been used as storage cell dielectrics to provide non-volatile memory. Ferroelectric materials change state substantially permanently in response to an applied electric field. For example, the ferroelectric material lead zirconate titanate (PZT), having a dielectric constant of 1000 and higher, permits a charge to be stored substantially permanently. Moreover, ferroelectric random access memory (FRAM) operates at power levels similar to conventional DRAM, and exhibits write speeds that are much faster than conventional non-volatile devices. Consequently, memory storage cells using ferroelectric capacitors can be fabricated into semiconductor memory devices with a simplified architecture and high packing density as compared to conventional non-volatile memory devices.
Ferroelectric storage capacitors do not store data in the form of charge, but instead store data by controlling the location of atoms within the crystal structure of the ferroelectric dielectric material. Write operations are largely similar to conventional DRAM-type devices as the atomic locations are manipulated by applying an electric field across the dielectric. Read operations, however, involve applying a potential across the dielectric and detecting the subsequent charge flow that results from the relocation of atoms within the crystal structure. When the applied field matches the stored state, little charge flows as little atomic relocation occurs. When the applied field is opposite that of the stored state, a significant charge flow occurs as the dielectric is essentially rewritten to the new state. Because these read operations are destructive, the state of the dielectric must be restored after a read operation.
The first designs with ferroelectric capacitors utilized memory cells containing two transistors and two ferroelectric capacitors, (“2T/2C”). Ferroelectric 2T/2C memory devices are described in the 1996 Ramtron International Corporation FRAM.RTM. Memory Products databook. 2T/2C memory cells are also described in U.S. Pat. No. 4,873,664 entitled “Self Restoring Ferroelectric Memory.”
More recently, ferroelectric memory cells have been fabricated that use a single transistor and single capacitor (“1T/1C”). These ferroelectric 1T/1C memory cells include a plate line and bit line that are oriented perpendicular to each other. These devices drive a heavy capacitive load of the cell plate line, resulting in lots of circuit overhead for plate line control.
U.S. Pat. No. 5,400,275 shows an alternative architecture for a 1T/1C memory cell where the bit lines and plate lines are parallel to each other, while the word lines are orthogonal to both. But, this architecture is not suitable for low voltage operation because it cannot apply a sufficient voltage to the ferroelectric capacitor during detecting and storing the polarization on the memory cell.
The conventional read operation has the bit line precharged to V=0 while a voltage is applied to the plate line. If the initial polarization state of the ferroelectric capacitor is negative (i.e., it is storing a “1”), the read operation switches the direction of the capacitor's polarization, and a relatively large signal develops on the bit line. In contrast, if the capacitor originally has positive polarization (i.e., storing a “0”), then the read operation does not change the capacitor's polarization, and a relatively small signal develops on the bit line. The read signal developed on the bit line is normally received by a sense amplifier which compares the signal to a reference voltage (V
ref
) to determine whether the capacitor stored a “0” (V
ref
>V
signal
) or a “1” (V
ref
<V
signal
).
When the bit lines and plate line are formed parallel to each other, a coupling capacitance develops between the lines. As the potential on the plate line changes during a read/write operation, the potential also changes on the bit lines due to the coupling capacitance. This potential drift on the bit lines can result in erroneous readings for the data stored by ferroelectric memory cells.
It is important that the bit line potential is affected only by the charge flow in the ferroelectric dielectric. However, when the bit lines and plate lines run in parallel, significant charge can be coupled from the plate line applied voltage to the bit lines, thereby making an accurate read operation more difficult.
FIG. 1
shows how conventional read/write operations, where the plate line
140
is charged from V=0 to V=V
DD
while the word line
120
is selected, causing the bit line
160
voltage to drift away from expected values for binary “0” and “1” signals developing on the bit line
160
, and bit lines of neighboring memory cells. The drift narrows the range of voltages V
signal
can have before erroneously crossing the V
ref
threshold. The reduced margin of error for V
signal
causes more false readings of the information in the memory cell being read, as well as neighboring memory cells.
The drift caused by precharging the plate line to V
DD
hinders the ability to simultaneously read or write to adjacent memory cells that share a common plate line. Thus, current semiconductor memory devices with 1T/1C, bit-plate parallel memory arrays do not simultaneously read from or write to adjacent memory cells that share a common plate line. These semiconductor memory devices read and write to a single memory cell at a time.
What is desired, therefore, is a 1T/1C, bit-plate parallel, ferroelectric memory architecture that provides high margin for read operations and is relatively immune from voltage drift in the read signal that develops on the bit line.
BRIEF SUMMARY OF THE INVENTION
The present invention includes a method for generating an informati
Hogan & Hartson L.L.P.
Le Vu A
Ramtron International Corporation
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