Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-12-19
2003-03-25
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S761000
Reexamination Certificate
active
06537919
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to chemical mechanical polishing (CMP) and surface finishes obtained therewith.
BACKGROUND OF THE INVENTION
As the number of layers in an integrated circuit has grown, so has the need for frequent planarizing steps. Most purely chemical methods for etching tend to follow the contours of the surface being etched and/claim or to selectively etch parts of heterogeneous surfaces. Purely mechanical methods for surface removal (i.e. polishing) tend to provide a planar etch front but, if all surface damage is to be eliminated, require slurries so fine as to reduce etch time to unacceptably low levels.
The CMP process represents an excellent compromise between the two approaches. It has been applied for STI (shallow trench isolation), pre-metal dielectric, inter metal dielectric (IMD), to cite a few examples. The more advanced the technology is, the more likely it is that CMP processes will be used. One disadvantage of CMP processes, however, is that complete elimination of all scratches is hard to achieve. This is illustrated schematically in
FIGS. 1 and 2
which show a substrate
11
on which are two protuberances
12
(typically metal lines) which have been over-coated with a layer
13
(typically a dielectric) resulting in an uneven top surface
14
. After CMP, surface
14
is now essentially planar except for the presence of micro-scratches
24
. By “micro-scratches” we imply that the scratches are no more than about 5,000 Angstroms deep.
From the FA (failure analysis) of products, the killing ratio for micro-scratches associated with CMP and other processes has been determined to be as much as 2 to 3% per layer. There is therefore strong motivation to eliminate this problem. Several methods had been tried to reduce such micro-scratches. For example, the slurry (abrasives), pad life, rotation speed, downward pressure (between wafer and pad), and oxide buffing have all been tried with varying degrees of success, with oxide buffing doing best. However, this latter approach turns out to be at the expense of range and uniformity.
The present invention discloses an approach that places no constraints on, and requires no changes to, the CMP process itself. Nor does it cause any reduction in range or uniformity. As will be seen, it can be applied in-situ or ex-situ, depending on the overall particular processing situation.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,180,525(Morgan) shows a CMP process involving scratches. U.S. Pat. No. 5,915,175 (Wise) reveals a process to reduce CMP induced damage. U.S. Pat. No. 6,110,795 (Liao) and U.S. Pat. No. 5,516,729 (Dawson et al.) show CMP/scratch related processes.
SUMMARY OF THE INVENTION
It has been an object of at least one embodiment of the present invention to provide a process whereby micro-scratches caused by cMP, or similar processing steps, may be removed.
Another object of at least one embodiment of the present invention has been that said process require little or no modification to the CMP, or similar, process itself.
Still another object of at least one embodiment of the present invention has been that said process be executable in in-situ or ex-situ modes.
These objects have been achieved by exposing the surface under treatment to a gas plasma after CMP (or other process that could produce micro-scratches) has been completed. Additionally, the invention discloses that the small amount of material that gets removed through exposure to the plasma may be replaced by deposition either in-situ or ex-situ. The added material may be the same as the removed material or a different material.
REFERENCES:
patent: 5516729 (1996-05-01), Dawson et al.
patent: 5915175 (1999-06-01), Wise
patent: 6110795 (2000-08-01), Liao
patent: 6180525 (2001-01-01), Morgan
patent: 6350694 (2002-02-01), Chang et al.
Ackerman Stephen B.
Ghyka Alexander
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Process to remove micro-scratches does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process to remove micro-scratches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process to remove micro-scratches will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3075400