Ferroelectric memory devices which utilize boosted plate...

Details Ferroelectric memory devices which utilize boosted plate... Ferroelectric memory devices which utilize boosted plate...

1998-09-08

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06198651

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices, and more particularly to nonvolatile integrated circuit memory devices and methods of operating nonvolatile integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Ferroelectric random access memory (FRAM) devices are “nonvolatile” memory devices because they preserve data stored therein even in the absence of a power supply signal. A FRAM device may comprise an array of ferroelectric memory cells and each ferroelectric memory cell in the array may be electrically coupled to a corresponding plate line PL, a corresponding word line WL and a corresponding bit line BL. Each ferroelectric memory cell may comprise an NMOS access transistor Tr and a ferroelectric capacitor C
F
electrically connected in series between a corresponding bit line BL and plate line PL, as illustrated by FIG.
1
. In addition, first and second electrodes of the ferroelectric capacitor C
F
may be electrically connected to a first source/drain region of the access transistor Tr and the plate line PL, respectively, a second source/drain region of the access transistor Tr may be electrically connected to a corresponding bit line BL and a gate electrode of the access transistor Tr may be electrically connected to a corresponding word line WL. The effective capacitance between the first source/drain region of the access transistor Tr and the ferroelectric capacitor C
F
may also be designated as C
jun
and the effective capacitance of the bit line BL may be designated as C
BL
. Typical FRAM devices are also described in an article by J. T. Evans, entitled “An Experimental 512-Bit Nonvolatile Memory with Ferroelectric Storage Cells”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1171-1175, October (1988).
The nonvolatile nature of a ferroelectric memory cell is a direct consequence of using a ferroelectric material as the dielectric of the cell's capacitor. Typical ferroelectric materials which can be used for the ferroelectric capacitor include Phase III potassium nitrate, bismuth titanate and lead zirconate titanate Pb(Zr, Ti)O
3
(PZT). Because these ferroelectric materials possess hysteresis characteristics, the polarity (i.e., state) of the ferroelectric material can be maintained even after interruption of the power supply. Thus, data (e.g., logic 0,1) can be stored in the FRAM as the polarity state of the ferroelectric material in each capacitor.
The typical hysteresis characteristics of a ferroelectric material will now be described in detail with reference to FIG.
2
. In
FIG. 2
, the abscissa represents a voltage V applied across the first and second electrodes of the ferroelectric capacitor, and the ordinate represents an amount of electric charge Q stored by the ferroelectric capacitor C
F
. Due to the hysteresis characteristic of the ferroelectric capacitor, current passing through the capacitor is changed by the history of the voltage applied thereto. For example, assuming that state B corresponds to data “1” and state D corresponds to data “0”, the state of the ferroelectric capacitor can be transferred from state B to state C and then to state D by application of a negative voltage pulse across the first and second electrodes (e.g., positive voltage to the plate line PL relative to the bit line BL when the access transistor Tr is turned-on). During this transition, the electric charge amount Q
R
accumulated in the ferroelectric capacitor is changed to −Q
R
. Accordingly, the total change in the accumulated charge becomes −2Q
R
, which means the voltage of the bit line BL is changed as shown in formula (1):
&Dgr;V
BL
=2Q
R
/C
BL
  (1)
However, in the event the ferroelectric capacitor is initially in state D corresponding to data “0”, and then a negative voltage pulse is applied, the ferroelectric capacitor will sweep from state D to state C and then back to state D, so any change in the potential of the bit line will essentially be negligible.
Now, assuming that an initial state of the ferroelectric capacitor is state D, if the voltage applied to the ferroelectric capacitor is increased, the state of the ferroelectric capacitor will transition from state D towards state A. If the intensity of the positive voltage applied to the ferroelectric capacitor is increased beyond a coercive voltage, the state of the ferroelectric capacitor will change from state D to state A. The removal of the positive voltage from a ferroelectric capacitor in state A will cause the capacitor to transition from state A to state B. Finally, if the voltage applied to a ferroelectric capacitor in state B is made sufficiently negative, the state of the ferroelectric capacitor will transition to state C. The removal of the negative voltage from a ferroelectric capacitor in state C will then cause the capacitor to transition from state C back to state D.
The polarization switching speed of a ferroelectric capacitor is approximately 10
−9
sec, and the necessary program time of the ferroelectric capacitor is typically shorter than that of other nonvolatile memory devices such as electrically programmable read only memory (EPROM) devices, electrically erasable and programmable read only memory (EEPROM) devices and flash memory devices. As will be understood by those skilled in the art, the read/write cycle endurance of a ferroelectric capacitor is typically on the order of 10
9
to 10
12
.
Techniques for reading data from and writing data to FRAM devices are disclosed in U.S. Pat. Nos. 4,873,664 to Eaton Jr., entitled “Self-Restoring Ferroelectric Memory”; U.S. Pat. No. 5,373,463 to Jones Jr., entitled “Ferroelectric Nonvolatile Random Access Memory Having Drive Line Segments”; U.S. Pat. No. 5,608,667 to Osawa, entitled “Ferroelectric Memory Automatically Generating Biasing Pulse for Plate Electrode”; U.S. Pat. No. 5,640,030 to Kenney, entitled “Double Dense Ferroelectric Capacitor Cell Memory”; and U.S. Pat. No. 5,751,626 to Seyyedy, entitled “Ferroelectric Memory Using Ferroelectric Reference Cells”. For example, U.S. Pat. No. 5,608,667 to Osawa discloses a FRAM device which utilizes a pulse generator
2
a
to automatically generate a plate line pulse signal having a predetermined pulse width, after enabling a word line potential. At
FIGS. 3-4
and the accompanying text, the '667 patent to Osawa also discloses the application of a plate line pulse signal having a magnitude of Vcc (i.e., the power supply potential) during both reading and writing operations.
Unfortunately, the use of a plate line pulse signal having a magnitude (V
P
) equal to Vcc during an operation to read the state of a ferroelectric memory cell may increase the likelihood of a reading error if the potential of the bit line BL is not significantly boosted. For example, assuming the magnitude of the plate line pulse signal is Vcc, then by voltage division the voltage V
F
that may appear across the ferroelectric capacitor during a read operation may be expressed as:
V
F
=V
P
(1−(C
F
/(C
F
+C
BL
)))  (2)
However, if the magnitude of V
F
is insufficient to enable a complete charge transfer of 2Q
R
when the memory cell is storing a data 1 value, errors may occur when sensing a potential of the bit line BL during a reading operation. Thus, notwithstanding the above-described FRAM devices, there continues to be a need for improved FRAM devices which are less susceptible to reliability failures caused by reading errors, for example.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit memory devices and methods of operating same.
It is another object of the present invention to provide nonvolatile integrated circuit memory devices having reduced susceptibility to reading errors and methods of operating same.
These and other objects, advantages and features of the present invention are provided by integrated circuit memory devices which comprise a plate line, a bit line, a ferroelectric memory cell containing a first ac

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