Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-31
2002-03-19
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S310000, C438S240000, C438S250000, C438S393000
Reexamination Certificate
active
06359295
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices and fabrication methods therefor, and more particularly to integrated circuit memory devices and fabrication methods therefor.
BACKGROUND OF THE INVENTION
Ferroelectric thin films have been used in nonvolatile memory devices to form ferroelectric memory devices. Ferroelectric memory devices utilize the spontaneous polarization phenomenon of a ferroelectric material to store information. High speed read/write operations may be accomplished with ferroelectric memory devices compared to conventional Erasable and Programmable Read Only Memories (EPROM) or Electrically Erasable and Programmable Read Only Memories (EEPROM).
Moreover, if a ferroelectric thin film is used as a dielectric layer in a cell capacitor of a Dynamic Random Access Memory (DRAM), a refresh operation may not be required, which can thereby reduce the power consumption of the DRAM and can improve the speed thereof. A ferroelectric memory device can perform read and write operations using a single power supply voltage similar to a Random Access Memory (RAM). Accordingly, ferroelectric memory devices are also referred to as Ferroelectric RAM (FRAM) devices.
FRAM devices may be classified into two categories based on the unit cells thereof. The first category includes devices having unit cells including a transistor in which the ferroelectric film is used as a gate insulating layer. The second category includes unit cells having an access transistor and a capacitor in which the ferroelectric film is used for the dielectric layer of the capacitor.
A FRAM in the first category, including a ferroelectric film as a gate insulating layer in a transistor, may have operational problems. For example, a silicon dioxide layer may be generated at the interface between a silicon substrate and the ferroelectric film which functions as a gate insulator due to a reaction between the silicon substrate and oxygen atoms. Moreover, it may be difficult to obtain high quality ferroelectric films due to the lattice constant difference or thermal expansion coefficient difference between the silicon substrate and the ferroelectric film.
For at least these reasons, FRAM devices of the second category have also been developed, in which the ferroelectric film is used as the dielectric layer of a cell capacitor. These devices may generally have a similar structure to a cell structure of a DRAM.
FIG. 1
is an equivalent circuit diagram of a conventional unit cell of a FRAM in which the ferroelectric film is used as the dielectric layer of the cell capacitor. In the circuit configuration shown in
FIG. 1
, the gate electrode G of an NMOS transistor T is connected to a word line W. The drain region D is connected to a bit line B, and the source region S is connected to one electrode of a ferroelectric capacitor C. The other electrode of the ferroelectric capacitor C is connected to a plate line P.
In conventional FRAM cells as described above, multiple masking steps and multiple conductive layers are generally used during fabrication. The use of multiple masking steps and multiple conductive layers may make it difficult to maintain alignment between layers and masking steps, and may thereby limit the integration density, cost and/or reliability of integrated circuit ferroelectric devices. Accordingly, there continues to be a need for integrated circuit ferroelectric memory device manufacturing methods and structures that can reduce the number of masking steps and/or conductive layers.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide integrated circuit ferroelectric memory manufacturing methods and structures that can reduce the number of masking steps.
It is another object of the present invention to provide integrated circuit ferroelectric memory manufacturing methods and structures that can reduce the number of separate conductive layers that need be used.
These and other objects are provided, according to the present invention, by methods of manufacturing integrated circuit ferroelectric memory devices wherein a first patterned conductive layer is formed on an integrated circuit substrate, to define a lower capacitor electrode and a gate electrode that is spaced apart therefrom. A source region and a drain region are formed on opposite sides of the gate electrode. A ferroelectric layer is formed on the lower capacitor electrode. An upper capacitor electrode is formed on the ferroelectric layer opposite the lower capacitor electrode, to thereby form a ferroelectric capacitor. Accordingly, the first patterned conductive layer is used to define both the lower capacitor electrodes and the gate electrodes for the integrated circuit ferroelectric memory device. It will be understood that the step of forming a source region and a drain region may precede the step of forming a first patterned conductive layer, such that the gate electrode is formed between the source region and the drain region.
The lower capacitor electrode preferably includes a lower capacitor electrode sidewall, and the gate electrode preferably includes a gate electrode sidewall. Between the steps of forming a first patterned conductive layer and forming a source region and a drain region, a lower capacitor electrode sidewall spacer and a gate electrode sidewall spacer are preferably formed on the lower capacitor electrode sidewall and on the gate electrode sidewall respectively. Between the steps of forming a ferroelectric layer and forming an upper capacitor electrode, an interlayer dielectric layer is preferably formed on the gate electrode, that exposes the lower electrode.
The first patterned conductive layer may be formed by forming an insulating layer on the integrated circuit substrate, forming a conductive layer on the insulating layer and patterning the conductive layer and the insulating layer, to form the first patterned conductive layer. Moreover, the conductive layer itself may be formed by forming a first conductive sublayer on the insulating layer and forming a second conductive sublayer on the first conductive sublayer. The second conductive sublayer, the first conductive sublayer and the insulating layer are then sequentially patterned, preferably using a single mask.
In another embodiment, the first patterned conductive layer defines a lower capacitor electrode and a pair of gate electrodes that are spaced apart from one another. A drain region is formed between the spaced apart gate electrodes and a pair of source regions is formed outside the gate electrodes on opposite sides thereof.
In forming a ferroelectric layer, the ferroelectric layer may be formed on the interlayer dielectric layer and on the exposed lower electrode, and then removed from the interlayer dielectric layer so that the ferroelectric layer only remains on the exposed lower electrode. The ferroelectric layer may be removed by chemical-mechanical polishing.
According to another aspect of the invention, the interlayer dielectric layer includes a sidewall on the lower electrode. Prior to forming the ferroelectric layer, a sidewall spacer is formed on the dielectric layer sidewall, to reduce diffusion from the ferroelectric layer. Moreover, a capping layer may be formed on the upper electrode to reduce diffusion from the ferroelectric layer through the upper electrode.
After forming the upper capacitor electrode, an interconnect layer is formed that electrically connects the top electrode and the source region. A bit line is formed that electrically contacts the drain region. Preferably, both the interconnect layer and the bit line are formed from the same conductive layer. More specifically, a second patterned conductive layer is formed on the source and drain regions and on the top electrode, to define an interconnect layer that electrically connects the top electrode and the source region and a bit line that electrically contacts the drain region. Thus, separate conductive layers need not be used for the top level interconnections. Prior to forming the second patterned conductive
Jung Dong-jin
Lee Mi-hyang
Chaudhuri Olik
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Weiss Howard
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