Ferroelectric memory devices

Details Ferroelectric memory devices Ferroelectric memory devices

2004-01-16

2004-09-28

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S532000

Reexamination Certificate

active

06798010

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory devices, and more particularly to ferroelectric memory devices and to methods of fabricating ferroelectric memory devices.
BACKGROUND OF THE INVENTION
Ferroelectric materials can obtain a magnetic polarization when exposed to an external electric field. The direction of the polarization can be controlled by changing the external electric field. When the external electric field is removed much of the polarization can remain in the ferroelectric materials. Examples of ferroelectric materials include PZT[Pb(Zi,Ti)O
3
], SBT[SrBi
2
Ta
2
O
9
] and other materials having a ferroelectric crystalline structure known as a perovskite structure. Memory devices which employ ferroelectric materials, such as ferroelectric random-access memories (FRAM), are widely used.
SUMMARY OF THE INVENTION
According to some embodiments of the present invention a ferroelectric memory device can include at least two bottom electrode patterns formed on a semiconductor substrate, a first ferroelectric layer disposed between the bottom electrode patterns, and a second ferroelectric layer formed over the bottom electrode patterns and the first ferroelectric layer. Top surfaces of the first ferroelectric layer and the bottom electrode patterns can be substantially aligned to provide a planarized surface on which the second ferroelectric layer can be formed. The first ferroelectric layer can also serve as a seed layer for creating a perovskite structure in the first and second ferroelectric layers for use as a capacitor in the ferroelectric memory device.
The ferroelectric memory device can further include an interlayer insulation layer on the semiconductor substrate with storage node contact plugs which pierce the interlayer insulation layer. The bottom electrode patterns can be formed on top of the interlayer insulation layer and electrically connected to the storage node contact plugs.
According to further embodiments of the present invention a method of fabricating a ferroelectric memory device can be provided. At least two bottom electrode patterns are formed on a semiconductor substrate. A first ferroelectric material layer is formed between the bottom electrode patterns. A second ferroelectric material layer is formed on a top surface of the first ferroelectric material layer and the bottom electrode patterns. The top surface of the first ferroelectric material layer can be substantially aligned with the top surface of the bottom electrode patterns.
In further embodiments of the fabrication method, a semiconductor device bottom structure such as a transistor is formed in the semiconductor substrate. An interlayer insulation layer is formed over the semiconductor substrate and patterned to expose a contact hole to the semiconductor substrate. A conductive layer is formed in the contact hole and etched to provide a contact plug in the contact hole. Another conductive layer is formed over the contact plug and patterned to form a capacitor bottom electrode pattern. The conductive layers can be formed of a noble metal of platinum and the like or an oxide or combination thereof. A ferroelectric material layer is formed on the semiconductor substrate to fill a space between the patterned bottom electrode patterns. The ferroelectric material layer is planarized to expose the top surface of the bottom electrode patterns and to leave a remnant ferroelectric material layer between the bottom electrode patterns. In this manner, top surfaces of the remnant ferroelectric material layer and the bottom electrode patterns are substantially aligned and providing a planarized surface therebetween. Another ferroelectric layer for a capacitor is formed on the remnant ferroelectric material layer and the top surface-exposed bottom electrode patterns.


REFERENCES:
patent: 5548157 (1996-08-01), Sakao et al.
patent: 5786259 (1998-07-01), Kang
patent: 6171925 (2001-01-01), Graettinger et al.
patent: 2002/0125524 (2002-09-01), Okudaira et al.
patent: 2002/0155659 (2002-10-01), Chen et al.

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