Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-30
2003-09-09
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06617628
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2000-69282, filed on Nov. 21, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a semiconductor device and a method of fabricating the semiconductor device. More specifically, the present invention is directed to a ferroelectric memory device and a method of fabricating the ferroelectric memory device.
BACKGROUND OF THE INVENTION
A ferroelectric memory device is a non-volatile memory device in which data can be stored even when power to the device is turned off. Similar to a dynamic random access memory (DRAM), a unit cell of the ferroelectric memory device is composed of one transistor and one capacitor. With an operating speed similar to that of a DRAM, the ferroelectric memory device can be highly integrated. Therefore, the ferroelectric memory device has been regarded as a next-generation non-volatile memory device.
A ferroelectric layer is used as a dielectric layer of a capacitor to achieve non-volatility in a ferroelectric memory device. The ferroelectric layer has a polarization hysteresis characteristic such that a polarity is maintained, even after a polarizing electric field has been removed.
Conventionally, a ferroelectric capacitor is composed of a lower electrode, a ferroelectric layer, and electrode layer, which are sequentially stacked. As integration levels of semiconductor devices increase, the ferroelectric capacitor must exhibit higher capacitance without requiring more area on the semiconductor device.
Various methods have been suggested to achieve higher capacitance. For example, a ferroelectric material having a higher polarization value is used, or the effective area of a capacitor is increased. One proposed to fabricate a three-dimensional (e.g., cylindrical or trench-shaped) capacitor. But a deposition method for forming an electrode or dielectric layer having a three-dimensional shape is not developed yet.
Therefore, the present invention is aimed at solving the foregoing problems and its object is to provide a ferroelectric memory device that can maximize the capacitance of a capacitor.
Another object of the present invention is to provide a ferroelectric memory device, that can enhance an integration level.
Still another object of the present invention is to provide a method of fabricating the above ferroelectric memory device.
SUMMARY OF THE INVENTION
To accomplish these and other objects of the present invention, a ferroelectric memory device includes first and second switching elements formed on a semiconductor substrate, an interlayer insulating layer formed on a resulting structure where the first and second switching elements are formed, and first and second ferroelectric capacitors, sequentially stacked on the interlayer insulating layer, each having at least three electrode layers. The first ferroelectric capacitor includes a lower electrode formed on the interlayer insulating layer, a first ferroelectric layer formed on the lower electrode, and a middle electrode formed on the first ferroelectric layer. The second ferroelectric capacitor includes the middle electrode, a second ferroelectric layer formed on the middle electrode, and an upper electrode formed on the second ferroelectric layer.
The first and second switching elements are first and second MOS transistors, respectively. In one embodiment, the lower electrode is electrically connected to a source region of the first MOS transistor. The upper electrode is electrically connected to a source region of the second MOS transistor, and further includes a plate line coupled to the middle electrode. Alternatively, the middle electrode is electrically connected to one of the source regions of the first and second MOS transistors, and further includes first and second plate lines that are coupled to the lower and upper electrodes, respectively. Alternatively, the lower and upper electrodes are electrically connected to one of the source regions of the first and second MOS transistors, and include a plate line coupled to the middle electrode.
According to a first aspect of the present invention, there is provided a method of fabricating a ferroelectric memory device. First and second switching elements are formed on a semiconductor substrate. An interlayer insulating layer is formed to cover the first and second switching elements. First and second contact plugs, which are respectively connected to the first and second switching elements, are formed in the interlayer insulating layer. On the interlayer insulating layer, a capacitor is formed wherein a lower electrode coupled to the first contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode are sequentially stacked. An insulating layer is formed to cover the capacitor, the second contact plug, and the interlayer insulating layer. In the insulating layer, an interconnection is formed to connect the second contact plug to the upper electrode. Further, a plate line coupled to the middle electrode is formed in the insulating layer.
According to a second aspect of the present invention, there is provided a method of fabricating a ferroelectric memory device. A switching element is formed on a semiconductor substrate. An interlayer insulating layer is formed to cover the switching element. A contact plug coupled to the switching element is formed in the interlayer insulating layer. On the interlayer insulating layer, a capacitor is formed wherein a lower electrode, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, an upper electrode are sequentially stacked. An insulating layer is formed to cover the capacitor, the contact plug, and the interlayer insulating layer. In the insulating layer, an interconnection is formed to connect the contact plug to the middle electrode.
According to a third aspect of the present invention, there is a provided a method of fabricating a ferroelectric memory device. A switching element is formed on a semiconductor substrate. An interlayer insulating layer is formed to cover the switching element. A contact plug coupled to the switching element is formed in the interlayer insulating layer. On the interlayer insulating layer, a capacitor is formed wherein a lower electrode coupled to the contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode are sequentially stacked. An insulating layer is formed to cover the capacitor and the interlayer insulating layer. In the insulating layer, an interconnection is formed to connect the lower electrode to the upper electrode. Further, a plate line coupled to the middle electrode is formed in the insulating layer.
A further understanding of the nature and advantage of the invention herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 5138412 (1992-08-01), Hieda et al.
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5903492 (1999-05-01), Takashima
Marger & Johnson & McCollom, P.C.
Nguyen Cuong Quang
Samsung Electronics Co,. Ltd.
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