Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

1999-06-18

2001-01-09

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S303000, C257S310000

Reexamination Certificate

active

06172386

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device and, more particularly, to a ferroelectric memory device as well as a method of fabrication a ferroelectric memory device.
2. Description of the Related Art
A requirement of modern data processing systems is that a substantial portion of the information stored in memory be randomly accessible to ensure rapid access to such information. Due to the high speed operation of memories implemented in semiconductor technologies, ferroelectric random access memories (FRAMs) have been developed which exhibit a significant advantage of being non-volatile. This non-volatility of FRAMs is achieved by virtue of the fact that a ferroelectric capacitor includes a pair of capacitor plates with a ferroelectric material between them having two different stable polarization states, which can be defined with a hysteresis loop depicted by plotting the polarization against applied voltage.
Recently, the use of such ferroelectric materials has reached commercial applications in the semiconductor industry. Ferroelectric memory elements are non-volatile, are programmable with a low voltage, e.g., less than 5 V, whereas typical flash memories are programmed at 18-22 V, have fast access times on the order of less than a nano-second, whereas typical flash memories have access times on the order of a micro-second, and are robust with respect to virtually unlimited numbers of read and write cycles. These memory elements also consume low power, less than 1 micro-ampere of standby current, and exhibit radiation hardness.
Ferroelectric materials which have allowed this breakthrough in integrated circuit applications include perovskite structure ferroelectric dielectric compounds, such as lead zirconate titanate PbZr
x
Ti
1−x
O
3
(PZT), barium strontium titanate (BST), PLZT (lead lanthanum zirconate titanate), and SBT (strontium bismuth tantalum).
In a ferroelectric memory fabrication process, it is a key point to obtain ferroelectric characteristics without any degradations, as well as a one capacitor/one transistor structure and a multi-level metal structure. Particularly in the case of a PZT, the ferroelectric characteristics are directly related to the amounts of perovskite crystalline structure produced by post-deposition annealing. Since a PZT film is formed in a heterogeneous manner, formation of the perovskite crystalline structure by post-deposition annealing is greatly affected by the material in contact therewith, such as capacitor electrodes (i.e., the lower electrode and the upper electrode). In particular, a platinum catalyses reduction reaction easily oxidizes the PZT, thereby causing unacceptable defects in the interface between the electrodes and the PZT as well as causing a deficit in the amount of titanium, which is easily oxidized, in the PZT, and which eventually results in reliability concerns.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above. Accordingly, a method consistent with the present invention provides for fabricating a ferroelectric memory device with improved ferroelectric characteristics, such as high temperature retention and high read/write endurance.
In accordance with one aspect of the invention there is provided a method for fabricating a ferroelectric memory device which includes forming a first insulating layer over a semiconductor substrate. A plurality of running transistors have already been formed on active regions in and on the semiconductor substrate. Each transistor includes a gate electrode with an insulating capping layer and a pair of source/drain regions extending from lateral edges of the gate electrode and within the active region to a predetermined depth.
A ferroelectric capacitor family is formed over the first insulating layer. The ferroelectric capacitor family includes a lower electrode, a ferroelectric film, and an upper electrode in that order from the first insulating layer. An adhesion/barrier layer can be further formed below the lower electrode. The adhesion/barrier layer is made of a material, such as titanium dioxide (TiO
2
). The lower electrode is made of a multi-layer with a conductive oxide electrode and a platinum electrode. The conductive oxide electrode is made of, for example, iridium dioxide (IrO
2
), using a DC magnetron sputtering technique. The platinum electrode is used to advantageously provide a favorable crystalline structure for ferroelectric film deposition. Other suitable electrodes may also be used.
The ferroelectric film can be made of PZT (lead zirconate titanium). The resulting PZT ferroelectric film has a relatively larger amount of titanium as compared to zirconate. For example, the composition of titanium to zinconate can be about 3:2, 7:3, or 4:1. The upper electrode can be made of a multi-layer of iridium dioxide and iridium in the order. A photolithographic process is carried out to form the ferroelectric capacitor. After patterning the capacitor, a diffusion barrier layer is formed to cover the ferroelectric capacitor.
The next process sequence is to form an interconnection. A second interlayer insulating layer is formed over the resulting structure. A first opening is formed in the second interlayer insulating layer and the diffusion barrier layer to the lower electrode. To minimize a catalytic effect of the platinum electrode as a reductive agent on the PZT film, a heat treatment can be carried out in an oxygen ambient at about 450° C. through a rapid thermal anneal process or using a furnace. This oxygen ambient heat treatment helps stabilize the iridium dioxide electrode formation, minimize defects at the interface between the ferroelectric film and the lower electrode, and minimize the stress variation of the iridium dioxide electrode. A first reaction barrier layer is formed in the first opening and over the second interlayer insulating layer. A second opening is formed in the barrier layer and the second and first interlayer insulating layers to the source/drain region. A second reaction barrier layer is formed over the resulting structure, and then a main metal layer is deposited thereover.


REFERENCES:
patent: 5475248 (1995-12-01), Takenaka
patent: 5481490 (1996-01-01), Watanabe et al.

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