Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-30
2004-04-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S068000, C257S071000, C257S296000, C257S298000, C438S003000, C438S240000
Reexamination Certificate
active
06717196
ABSTRACT:
RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-56392, filed on Sep. 13, 2001, the contents of which are herein incorporated by this reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device having a ferroelectric capacitor that form a storage cell in a ferroelectric random access memory (FRAM) and to a method of forming the same.
BACKGROUND OF THE INVENTION
When an external electric field is applied to a ferroelectric substance, a polarization is generated in the ferroelectric substance. After the external electric field is removed, the polarization nevertheless remains broadly therein. Direction of a self-polarization therein can be controlled by changing the external electric field. The ferroelectric substance may be formed by processing a high-dielectric substance such as PZT (Pb(Zi,Ti)O3) or SBT (SrBi2Ta2O9). These properties of the ferroelectric substance are similar to the basic principle on which a conventional, widely-used binary memory operates.
In order to form a ferroelectric cell, a high-dielectric substance such as PZT or SBT is used, the substance having a ferroelectric crystalline structure called “perovskite structure”. In a conventional method of forming the perovskite structure, a high-dielectric substance is stacked in an amorphous state, heated to about 700° C. in an ambient for oxidization, and crystallized. However, even after the perovskite structure is formed, if a physical impact is applied thereto by anisotropic etching in a subsequent process, or if a certain material such as hydrogen penetrates into the ferroelectric layer by diffusion, a serious inferiority in the properties of the ferroelectric substance may result. Fortunately, such inferiority of the resulting ferroelectric layer may be cured by an annealing process in an oxygen ambient.
When the perovskite structure is formed, or when the subsequent inferiority of the ferroelectric layer is cured, the process condition requires an oxygen ambient and high temperature. If a material such as polysilicon is used to form capacitor electrodes on and under the ferroelectric layer, at least the surface or the interface is oxidized, adversely affecting conductivity and capacitance. Thus, platinum, iridium or another noble metal is conventionally used so that the ferroelectric capacitor does not form an insulating oxide layer at a capacitor electrode contacting with the ferroelectric layer under the ambient of oxidation and at a high temperature.
FIGS. 1 and 2
are cross-sectional views illustrating the process of forming ferroelectric capacitors having planar structures frequently employed in a conventional ferroelectric memory device.
In
FIG. 1
, the ends of a lower electrode
16
, a ferroelectric pattern
18
, and an upper electrode
20
are stair-stepped, and this indicates that each layer has been formed through a separate patterning process. Referring to
FIG. 1
, the lower electrode layer, ferroelectric layer and upper electrode layer are sequentially stacked on an interlayer dielectric layer
12
where a capacitor lower electrode contact
14
is formed. These three layers are patterned through photolithography and etching processes to form lower electrode
16
, ferroelectric pattern
18
and upper electrode
20
. However, a photoresist pattern used for patterning and the noble metal layers composing each electrode layer have almost the same etch rate. Thus, they are patterned not by one photolithography process but by three successive photolithography processes.
FIG. 2
shows a similar pattern with FIG.
1
. In
FIG. 2
, an upper electrode
20
is formed by being patterned through additional photolithography and etching processes, and a ferroelectric pattern
18
and a lower electrode
16
are formed by being patterned continuously using the same photoresist pattern (not illustrated). Thus, in this case, the photolithography process is performed twice to form the capacitor.
When a ferroelectric capacitor having a conventional planar structure is formed, it is difficult to form the entire capacitor structure by one photolithography process. Thus, the process of forming a ferroelectric capacitor becomes complicated and the cost is increased. Moreover, failure may occur during the photolithography process. Also, because the ferroelectric capacitor has a simply planar structure, increasing capacitance per unit area is difficult.
FIGS. 3 and 4
illustrate conventional ferroelectric memory devices for overcoming the limitation in the capacitance of capacitors having simple planar structures, as disclosed in the U.S. Pat. Nos. 6,043,526 and 5,499,207, respectively.
Referring to
FIG. 3
, an interlayer dielectric layer
12
is stacked at a semiconductor substrate
10
having a bit line
23
and a MOS transistor composed of a gate electrode
31
and source/drain regions
15
, and then interlayer dielectric layer
12
is planarized. A contact
14
is formed through the interlayer dielectric layer
12
to connect a capacitor lower electrode
35
with a source region of the transistor. A cylindrical lower electrode
35
is formed on the contact
14
. A barrier layer, a ferroelectric layer and an upper electrode layer are stacked by a CVD technique on the semiconductor substrate where the lower electrode
35
is formed. These layers are patterned to form an upper electrode
43
, a ferroelectric pattern
41
and a barrier pattern
38
. Thus, a three-dimensional ferroelectric capacitor is formed. However, even in this prior art case, two exposing processes are required, one to pattern the lower electrode layer and another to pattern the upper electrode layer and the ferroelectric layer. Also, since the lower and upper electrodes are of noble metal, when they are etched together, their profiles are not good.
Referring to
FIG. 4
, an interlayer dielectric layer
12
is formed at a semiconductor substrate
10
having the lower structure, and a contact plug
14
is formed through the interlayer dielectric layer
12
. A cylindrical lower electrode
35
is formed to cover the contact plug
14
. Although not shown in
FIG. 4
, the lower electrode
35
is over-etched during patterning and the top of the interlayer dielectric layer
12
may be selectively etched to a certain depth. A conformal CVD ferroelectric layer
41
and a thick CVD upper electrode
43
are stacked over the entire surface of the semiconductor substrate
10
. In this case, the upper electrode
43
is a wide-plate type that may produce parasitic capacitance and unreliable operation in a semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a ferroelectric memory device which decreases the number of photolithography processes to simplify the entire process when a ferroelectric capacitor is formed, and a method of forming the same. It is another object of the present invention to provide a ferroelectric memory device having a ferroelectric capacitor that has a larger capacitance per a unit area in comparison with a conventional ferroelectric capacitor having a planar structure.
The present invention is directed to a ferroelectric memory device including a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure, and the capacitor lower electrode is formed into a cylindrical or rod shape having a certain height above the semiconductor substrate having the lower structure. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The upper electrode has a spacer shape and is formed on the ferroelectric layer around the sidewall of the capacitor lower electrode.
A hard mask pattern may be formed on the capacitor lower electrode for patterning the lower electrode. The hard mask pattern is mostly of silicon oxide and the thickness thereof is preferably thinner than half the height of the lower electrode.
Pl
Marger & Johnson & McCollom, P.C.
Nelms David
Samsung Electronics Co,. Ltd.
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