Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-21
2003-12-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06664158
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated ferroelectric memory configuration and to a method for producing the configuration, in which the memory cells are arranged using the stacking principle and in which both of the capacitor electrodes, which are located one above the other, of each memory cell are directly connected to the corresponding source and drain region of the associated selection transistor in the substrate by contact plugs.
A specific configuration of memory cells for ferroelectric memories has been proposed by D. Takashima et al. in a specialist report: “High-Density Chain Ferroelectric Random Access Memory (Chain FRAM)” in IEEE Journal of Solid State Circuits, Volume 33, No. 5, May 1998, page 787, and in a further specialist report “A sub-40 ns Random Access Chain FRAM Architecture with a 7 ns Cell-Plate-Line Drive” in IEEE International Solid-State Circuits Conference, 1999.
When using stacking cells, both capacitor electrodes are connected directly to the corresponding source/drain regions of the associated selection transistor in the substrate. This configuration of stacking cells is highly space-saving, in contrast to offset cells, in which the capacitor is located alongside, and not above, the transistor, and the capacitor electrodes must each be connected via a metal layer.
In chain FRAMs, since the memory cells are arranged not only between the lower electrode and the substrate but also between the upper electrode and the substrate, electrical contacts must be produced in the form of contact plugs. Since these two contact plugs have to produce contact connections for different electrode layers, they cannot be produced in the same process step. In particular, the contact plug for the upper electrode is problematic, since the insulating memory dielectric is located under that electrode. This dielectric must be removed for electrical contact, which involves lithography directly on the dielectric. However, in general, this should be avoided since, in consequence, the interface between the dielectric and the upper electrode can be contaminated, and this degrades the electrical characteristics of the capacitor.
FIG. 3
shows a circuit configuration in the form of a chain FRAM including four memory cells <
0
>, <
1
>, <
2
> and <
3
>. Each memory cell includes a ferroelectric capacitor C
ferro
and a selection transistor connected in parallel with it. The gate electrode of each selection transistor is connected to a respective word line WL
0
-WL
3
. Such a chain is selected by means of a common block select transistor using a selection signal BS. The drain or source area of the block select transistor is connected to the bit line BL. It is, of course, also possible to interconnect a different number of cells, for example 2, 8, 16 or 32 FRAM cells, to form a chain.
FIG. 4
a
is a schematic planar view and
FIGS. 4
b
-
4
d
are cross-sectional views illustrating how the contact plugs would be produced using conventional methods.
FIG. 4
c
shows the layer structure with planar capacitors, with the upper electrode plates being annotated by the reference number
2
, the lower electrode plates by
4
and the dielectric by
3
. The cross-sectional illustration shown in
FIG. 4
d
shows the construction with capacitors having a three-dimensional lower electrode. The lower electrode includes an electrode strip
4
s
and stud-like projections
4
. The dielectric
3
covers the electrode strip
4
s
and the stud-like projections
4
, while the upper electrode plate
2
, which is three-dimensional, covers the stud-like projection
4
on the lower capacitor electrode.
FIGS. 4
a
and
4
b
show a planar plan view and a cross sectional view, respectively, of a chain of two FRAM memory cells <
0
> and <
1
> with three-dimensional capacitors constructed as the capacitor shown in
FIG. 4
d
. During the production of such a memory cell chain, first the contact plugs
5
for the lower electrode, that is to say for the electrode strip
4
s
, are etched and filled; the lower electrode, including the electrode strip
4
s
and the stud-like projection
4
are then deposited, with the contact plugs
5
allowing electrical contact with the substrate, that is to say with the source or drain area of the selection transistor. The dielectric
3
is then deposited over the lower capacitor
4
,
4
s
, and this dielectric
3
must be removed in the area of the later produced contact plugs
6
for the upper electrode
2
(see the insulating areas
9
). Lithography performed directly on the dielectric
3
is required to remove the dielectric
3
. The upper capacitor electrode
2
is then deposited, with the electrical contact being produced by the contact plug
6
for the substrate, that is to say for the source or drain area of the associated selection transistor.
FIG. 4
a
also shows that the plan area occupied by one memory cell, for example <
0
>, is 10.5 F
2
=3 F×3.5 F. In this case, F indicates the minimum feature size. In
FIG. 4
b
, the word lines WL are denoted by the reference number
7
.
Thus, in order to produce the contact plug
6
for the upper capacitor electrode
2
, the lower electrode, that is to say the electrode strip
4
s
thereof, and the dielectric must be removed in the areas, denoted by
9
, around the contact plug
6
, so that the subsequently deposited upper electrode
2
makes good electrical contact with the plug
6
. As mentioned, this is disadvantageous, since the boundary area between the dielectric and the upper electrode can be contaminated.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide an integrated ferroelectric memory configuration such that there is no need to structure the dielectric before deposition of the upper capacitor electrode.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing an integrated ferroelectric memory configuration, that includes steps of: configuring memory cells using a stacking principle; for each one of the memory cells, providing a capacitor having two capacitor electrodes that are located one above another and providing an associated selection transistor that is located in a substrate; for each one of the memory cells, using contact plugs to directly electrically connect the two capacitor electrodes to a source region and a drain region of the associated selection transistor; producing given ones of the contact plugs from above; and providing each of the given ones of the contact plugs for contact connecting an upper one of the capacitor electrodes of the capacitor of at least one of the memory cells.
In accordance with an added mode of the invention, the method includes: in a first step, for the capacitor of each one of the memory cells, first producing one of the contact plugs for a lower one of the capacitor electrodes and then producing a dielectric; in a second step, for the capacitor of each one of the memory cells, etching a contact hole from above, through the upper one of the capacitor electrodes and at least through the dielectric as far as a substrate area of the associated selection transistor; the contact hole being for one of the given ones of the contact plugs for contact connecting an upper one of the capacitor electrodes; and in a third step, for the capacitor of each one of the memory cells, producing the one of the given ones of the contact plugs from above by filling the contact hole with a highly conductive metallic material to form an electrically conductive connection between the upper one of the capacitor electrodes and the substrate area of the associated selection transistor.
In accordance with an additional mode
Dehm Christine
Hönigschmid Heinz
Röhr Thomas
Greenberg Laurence A.
Hoang Quoc
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
LandOfFree
Ferroelectric memory configuration and a method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ferroelectric memory configuration and a method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory configuration and a method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3184274