Ferroelectric memory and method of operating same

Details Ferroelectric memory and method of operating same Ferroelectric memory and method of operating same

1999-08-30

2002-04-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06373743

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to ferroelectric memories, and more particularly to such a memory utilizing such ferroelectric field effect transistors and methods of operating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950's that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello et al., “The Physics of Ferroelectric Memories”,
Physics Today
, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. However, it has been postulated for at least 40 years that it may be possible to design a memory in which the memory element is a ferroelectric field effect transistor (FET), which memory could be non-destructively read. See Shu-Yau Wu, “A New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistor”, IEEE Transactions On Electron Devices, pp. 499-504, August 1974; S. Y. Wu, “Memory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistors”,
Ferroelectrics
, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C. A. Paz De Araujo, and L. D. McMillan, “Integrated Ferroelectrics”,
Condensed Matter News
, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary, single state effect rather than a long lived two-state effect, it is now believed that this effect was charge injection effect rather than an effect due to ferroelectric switching. However, a metal-ferroelectric-insulator-semiconductor FET device, i.e. a MFISFET, has recently been reported that appears to show true ferroelectric memory behavior. See Tadahiko Hirai, et al., “Formation of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO
2
Buffer Layer”,
Japan Journal of Applied Physics
, Vol. 33, Part I, No. 9B, pp. 5219-5222, September 1994; Tadahiko Hirai et al., “Characterization of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO
2
Buffer Layer”,
Japan Journal of Applied Physics
, Vol.34, Part I, No. 8A, pp. 4163-4166, August 1995; Yong Tae Kim et al., “Memory Window of Pt/SrBi
2
Ta
2
O
9
/CeO
2
/SiO
2
/Si Structure For Metal Ferroelectric Insulator Semiconductor Field Effect Transistor”,
Applied Physics Letters
, Vol.71 No. 24, pp. 3507-3509, Dec. 15, 1997; and U.S. Pat. No. 5,744,374 issued Apr. 28, 1998 to Jong Moon.
To make a memory requires not only a memory element, but also a means for addressing a large number of memory elements. Initially, it was believed that a ferroelectric memory element might be addressed by a simple array of rows and columns of conductors. A ferroelectric memory element, it was thought, could be located at each of the junctures of the array and addressed by applying a voltage to the conductors for the corresponding row and column. It was believed that if the voltage on each conductor was less than the threshold voltage for ferroelectric switching (coercive voltage) and the voltage difference between the conductors was greater than the coercive voltage, then only the selected cell would be written to or read, and the other cells would remain unchanged. However, it was found that this did not work because the neighboring unselected cells were disturbed by the voltages on the address lines. Thus, a switch was added between one of the address lines and each ferroelectric memory element. See U.S. Pat. No.2,876,436 issued Mar. 3, 1959 to J. R. Anderson and U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton, Jr. If the switch is a transistor as in the latter patent, the memory assumes a memory address architecture essentially the same as that of a conventional DRAM. However, when applied to a ferroelectric memory, even this architecture disturbed the memory cells attached to the same plate line as the addressed cell. That is, it has been found that ferroelectric materials do not have a sharp coercive threshold voltage, but rather even a small voltage will cause the ferroelectric to partially switch and, therefore, the repetitive application of small disturb voltages, such as occur in a conventional memory array, eventually causes the change or loss of a memory state. Therefore, a more complex architecture was proposed to overcome this disturb. See, for example, U.S. Pat. No. 4,888,733 issued Dec. 19, 1989 to Kenneth J. Mobley.
The above address schemes are all for a NVFRAM; that is, a memory utilizing a ferroelectric capacitor as a memory element, rather than for a memory utilizing a ferroelectric FET. A number of address architectures have been disclosed up to now for a memory in which the memory element is a ferroelectric FET. U.S. Pat. No. 5,523,964 issued Jun. 4, 1996 to McMillan et al., discloses a relatively complex addressing architecture, utilizing five transistors in each memory cell in addition to the ferroelectric FET. This complexity is incorporate to, like the Mobley et al. architecture, to avoid the disturb problem. Such complex architecture results in a memory that is much less dense and slower than, for example, a conventional DRAM. An architecture that uses one ferroelectric FET per memory cell has been proposed, but has not been implemented because it cannot be read properly if three neighboring cells all are in the conducting logic state. See, U.S. Pat. No. 5,449,935 issued to Takashi Nakamura on Sep. 12, 1995, col. 3, line 56-col. 4, line 15. Another such one-FET-per-memory cell design has been proposed in U.S. Pat. No. 5,768,185 issued to Takashi Nakamura and Yuichi Nakao on Jun. 16, 1998. However, during reading a voltage of 3 volts to 5 volts is applied to the word line while the ground or zero volts is applied to the bit line. While this is not enough to switch the ferroelectric in a single read cycle, as indicated above, it is now known that successive pulses of this magnitude, such as occur in a memory in the normal process of reading, can disturb the ferroelectric state. In addition, since the bit line is connected to the source and substrate and the word line is connected to the gate, it the WLn and BLm+
1
signals are not exactly synchronized, the erase process of one cell will disturb the next. Under manufacturing specifications that are practically feasible, such exact synchronization is difficult to achieve in all cells. Therefore, in a commercial product there will short disturb voltages during the erase cycle also. Further, with this architecture, it is not possible to write a byte at a time, which is a much faster way of reading in a ferroelectric FET. Thus, it appears that the fact that the ferroelectric material does not have a sharp coercive field threshold and can be switched by repetitive applications of a small voltage has made several of the original objectives of research into ferroelectric memories unattainable. It would, therefore, be highly desirable to provide an architecture and method for addressing a ferroelectric memory, particularly a ferroelectric FET structure and method of making the structure, that was relatively simple and, at the same time, avoided the problems in the prior art, such as the disturb problem.
SUMMARY OF THE INVENTION
The invention solves the above problem by providing a method and apparatus for addressing a ferroelectric memory in which each memory cell preferably contains only the ferroelectric memory element, e.g., a ferroelectric FET.
In one aspect the invention comprises placing the source/drains of the non-selected memory cells n a high resistance or open state.
Another aspect of the invention comprises placing the gates of both the selected and non-selected cells in a high resistance or open state during the read cycle.
Another aspect of the invention comprise

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