Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-10
2002-01-15
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000
Reexamination Certificate
active
06339238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to ferroelectric field effect transistors, and more particularly to ferroelectric memories utilizing such transistors and methods of operating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950's that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello, et al., “The Physics of Ferroelectric Memories”,
Physics Today
, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. However, it has been postulated for at least 40 years that it may be possible to design a memory in which the memory element is a ferroelectric field effect transistor (FET), which memory could be non-destructively read. See Shu-Yau Wu, “A New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistor”, in
IEEE Transactions On Electron Devices
, pp. 499-504, August 1974; S. Y. Wu, “Memory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistors”, in
Ferroelectrics
, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C.A. Paz De Araujo, and L. D. McMillan, “Integrated Ferroelectrics”, in
Condensed Matter News
, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary, single state effect rather than a long lived two state effect, it is now believed that this effect was charge injection effect rather than an effect due to ferroelectric switching. However, recently a metal-ferroelectric-insulator-semiconductor FET device, i.e. a MFISFET, has been reported that appears to show true ferroelectric memory behavior. See Tadahiko Hirai, et al., “Formation of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO
2
Buffer Layer”, in
Japan Joumal of Applied Physics
, Vol. 33, Part I, No. 9B, pp. 5219-5222, September 1994; Tadahiko Hirai, et al., “Characterization of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO
2
Buffer Layer”, in
Japan Journal of Applied Physics
, Vol. 34, Part I, No. 8A, pp. 4163-4166, August 1995; Yong Tae Kim, et al., “Memory Window of Pt/SrBi
2
Ta
2
O
9
/CeO
2
/SiO
2
/Si Structure For Metal Ferroelectric Insulator Semiconductor Field Effect Transistor”,
Applied Physics
Letters, Vol. 71 No. 24, Dec. 15, 1997, pp. 3507-3509; and U.S. Pat. No. 5,744,374 issued Apr. 28, 1998 to Jong Moon.
To make a memory requires not only a memory element, but also a means for addressing a large number of memory elements. Initially, it was believed that a ferroelectric memory element might be addressed by a simple array of rows and columns of conductors. A ferroelectric memory element, it was thought, could be located at each of the junctures of the array and addressed by applying a voltage to the conductors for the corresponding row and column. It was believed that if the voltage on each conductor was less than the threshold voltage for ferroelectric switching (coercive voltage) and the voltage difference between the conductors was greater than the coercive voltage, then only the selected cell would be written to or read, and the other cells would remain unchanged. However, it was found that this did not work because the neighboring unselected cells were disturbed by the voltages on the address lines. Thus, a switch was added between one of the address lines and each ferroelectric memory element. See U.S. Pat. No. 2,876,436 issued on Mar. 3, 1959 to J. R. Anderson and U.S. Pat. No. 4,873,664 issued on Oct. 10, 1989 to S. Sheffield Eaton, Jr. If the switch is a transistor as in the latter patent, the memory assumes a memory address architecture essentially the same as that of a conventional DRAM. However, when applied to a ferroelectric memory, even this architecture disturbed the memory cells attached to the same plate line as the addressed cell. That is, it has been found that ferroelectric materials do not have a sharp coercive threshold voltage, but rather even a small voltage will cause the ferroelectric to partially switch and, therefore, the repetitive application of small disturb voltages, such as occur in a conventional memory array, eventually causes the change or loss of a memory state. Therefore, a more complex architecture was proposed to overcome this disturb. See, for example, U.S. Pat. No. 4,888,733 issued on Dec. 19, 1989 to Kenneth J. Mobley.
The above address schemes are all for a NVFRAM; that is, a memory utilizing a ferroelectric capacitor as a memory element, rather than for a memory utilizing a ferroelectric FET. Insofar as known to applicants, the only address architecture disclosed up to now for a memory in which the memory element is a ferroelectric FET is shown in
FIG. 1
of U.S. Pat. No. 5,523,964 issued on Jun. 4, 1996 to McMillan, et al. Like the Mobley, et al., architecture, to avoid the disturb problem, this architecture is relatively complex, utilizing five transistors in each memory cell in addition to the ferroelectric FET. Such complex architecture results in a memory that is much less dense and slower than, for example, a conventional DRAM. Thus, it appears that the fact that the ferroelectric material does not have a sharp coercive field threshold and can be switched by repetitive applications of a small voltage has made several of the original objectives of research into ferroelectric memories unattainable. It would, therefore, be highly desirable to provide a simpler architecture and method for addressing a ferroelectric memory.
SUMMARY OF THE INVENTION
The invention solves the above problem by providing a method and apparatus for addressing a ferroelectric memory in which there are no additional electric elements in the individual memory cell; that is, it provides an architecture in which each memory cell preferably contains only the ferroelectric memory element, e.g. the ferroelectric FET.
A memory cell can be written to by applying an electrical pulse to the gate and an electrical bias between another two electrical elements of the cell.
In the preferred embodiment, the ferroelectric memory element is a ferroelectric FET and a write bias is applied between the substrate and a FET source/drain.
In one preferred embodiment, a source/drain of all cells in an array are held at a common voltage and the substrate voltage is used to select the cells to be written to. Preferably, the drain voltage is used to select which logic state is to be written to an individual cell.
A truth table provides a unique drain to source current for each combination of write bias with the pulse on the gate. A unique logic state is associated with the unique drain to source current.
Preferably, the cell is read by sensing the source/drain current when a voltage difference is placed across the source and drain.
New ferroelectric memory cell structures and fabrication processes are also provided to ensure that the substrate of each cell can be electrically isolated from the substrate of the other cells.
The invention provides a method of writing to a selected memory cell in a ferroelectric memory, the memory including a plurality of memory cells each containing a ferroelectric FET, each of the ferroelectric FETs having a first electrical element and a second electrical element, the ferroelectric FETs arranged in an array comprising a plurality of rows and a plurality of columns of the ferroelectric FETs, the memory further including a plurality of first row lines, each of the first row lines running parallel to one of the rows of the ferroelectric FETs, and a plurality of column lines, each of the column lines running parallel to one of the columns of ferroelectric FETs, the method comprising placing a first voltage on the one of the
Cuchiaro Joseph D.
Joshi Vikram
Lim Myoungho
McMillan Larry D.
Paz de Araujo Carlos A.
Symetrix Corporation
Wojciechowicz Edward
LandOfFree
Ferroelectric field effect transistor, memory utilizing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ferroelectric field effect transistor, memory utilizing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric field effect transistor, memory utilizing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2868084