Ferroelectric capacitor memory

Details Ferroelectric capacitor memory Ferroelectric capacitor memory

2001-07-16

2003-02-25

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S203000

Reexamination Certificate

active

06525956

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a non-volatile ferroelectric memory for storing data by using characteristics of a ferrorelectric capacitor.
BACKGROUND ART
A non-volatile memory being capable of keeping data after the power is turned off has been achieved in recent years by using a ferroelectric material such as PZT as well that shows hysteresis characteristics. Namely, such a non-volatile memory is embodied with a simple configuration by using a ferroelectric material for a memory cell. A nonvolatility is exhibited by the characteristics of a ferroelectric capacitor, which is made of a ferroelectric material, to store digital data.
A ferroelectric RAM (FeRAM: Ferroelectric Random Access Memory) using such a non-volatile memory has the above non-volatile characteristics with a simple configuration and can perform a high-speed operation at a low voltage. Thus, the FeRAM has attracted interest as a ferroelectric memory from a number of memory chip manufacturers.
An operating speed of the FeRAM is determined by polarization inversion time of the ferroelectric capacitor. The polarization inversion time of the ferroelectric capacitor is determined by a capacitor area, a thickness of the ferroelectric thin film, an applied voltage, and so on. The polarization inversion time is normally indicated in ns.
The above-mentioned conventional ferroelectric memory will be described.
FIG. 7
is an explanatory drawing showing polarization characteristics of the ferroelectric capacitor in the conventional ferroelectric memory.
FIG. 7
also shows a hysteresis loop of the ferroelectric capacitor. A vertical axis indicates a charge quantity, which is induced on a surface of a ferroelectric by spontaneous polarization of the ferroelectric, that is, a polarization quantity [C]. A horizontal axis indicates a voltage [V] applied to the ferroelectric capacitor.
When a positive voltage is applied to the ferroelectric while the ferroelectric capacitor has an inter-terminal voltage of 0 and polarization does not occur, a polarization quantity increases from S to A in FIG.
7
. The ferroelectric does not increase in polarization quantity at a certain voltage (electric field) or more. Namely, a polarization quantity reaches a maximum value at point A.
Inclination at this point is defined as (Cs=dq/dV) where Cs represents a parallel plate capacitance component. Thereafter, even when an inter-terminal voltage of the ferroelectric capacitor is set at 0, a polarization quantity is not set at 0 but stays at H. Pr[C] represents a polarization charge quantity stored at this moment. This characteristic is used to form a non-volatile memory.
FIG. 9
is a circuit diagram showing the configuration of a ferroelectric memory including a typical 2T-type (2 transistors) 2C-type (2 capacitors) memory cell. In
FIG. 9
, reference character WL denotes a word line, reference characters BL and XBL denote bit lines, reference numerals
900
and
901
denote ferroelectric capacitors, reference numerals
902
and
903
denote selective transistors, reference numeral
904
denotes a transistor for pre-charging the bit lines BL and XBL to a VSS level, reference numeral
905
denotes an amplifier for amplifying a potential difference between the bit lines BL and XBL, reference numeral
906
denotes a an transistor for selectively connecting the bit lines BL and XBL and data lines DL and XDL, and reference character Cb denotes a parasitic capacitance of the bit lines BL and XBL.
Referring to a timing chart of
FIG. 10
, the following will discuss an operation of reading data from the ferroelectric memory having the above configuration.
BLDIS is deactivated to set the bit line BL/XBL to a floating state, the word line WL is activated at a VPP level, which is higher than a source voltage VDD, a memory cell is selected, and a cell plate line CP is activated. Thus, a voltage VDD is applied to the ferrorelectric capacitors
900
and
901
. It is assumed that the memory cell
900
stores Hi data and the memory cell
901
stores Low data. Further, a potential Vbl and Vxbl of the bit line BL/XBL and a potential difference Vdif of the bit line BL/XBL are approximately indicated by the following equation.
Vbl=VDD
/(
Cb/Cs
+1)
 
Vxbl=VDD
/(
Cb/Cs
+1)+(2
Pr/Cs
)/(
Cb/Cs
+1)
Vdif=Vxbl−Vbl=
(2
Pr/Cs
)/(
Cb/Cs
+1)  (1)
Subsequently, SAP is activated while SAN is deactivated to activate a sense amplifier, and a bit line potential is amplified. YSW is activated to transfer information of the bit line BL/XBL to the data line DL/XDL. Next, the cell plate line CP is deactivated to rewrite Low data of the memory cell
901
, YSW is deactivated, SAP is deactivated, SAN is activated, the sense amplifier is deactivated, and BLDIS is activated to pre-charge the bit line BL/XBL to a VSS level. After the bit line BL/XBL is pre-charged to a VSS level, the word line WL is deactivated and the reading cycle is completed.
In Equation (1), a reading potential increases as a parasitic capacitance Cb decreases. However in reality, its polarization charge quantity Pr[C] reduces a bit line potential of a floating state, a voltage is not sufficiently applied to the ferroelectric capacitors, and a polarization charge quantity for writing cannot be taken out from the memory cell.
Moreover, in the case where 2Pr is raised according to an increased area of the ferroelectric capacitor and a thinner film of the ferroelectric, Cs also increases and a voltage applied to the ferroelectric capacitor is reduced as mentioned above. Consequently, a polarization charge quantity for writing cannot be taken out from the memory cell.
Therefore, a reading potential difference of the bit line BL/XBL is given a peak value by Cb/Cs. The relationship between a bit line output potential difference [V] and Cb/Cs is shown in FIG.
8
.
Also, a polarization charge quantity 2Pr of the ferroelectric is reduced by deterioration of the ferroelectric. Hence, even when Cb/Cs is set to maximize a reading potential of the bit line BL/XBL, a problem occurs on reliability because 2Pr is reduced by deterioration of the ferroelectric, a reading potential difference to the bit line BL/XBL decreases, and reading failure is likely to occur.
As described above, the conventional ferroelectric memory requires a sufficient reading margin to positively read data during the reading operation. Even if a capacitor area is simply increased, it is difficult to completely take out a charge quantity, which has been stored in the ferroelectric upon writing, during the reading operation, resulting in a limit on an obtained reading margin.
Additionally, even when Cb/Cs is set to maximize a bit line reading potential difference, 2Pr is reduced by deterioration of the ferroelectric, Cb/Cs is varied from an optimum value, a reading potential difference of the bit line is reduced largely, reading failure is more likely to occur, and data cannot be read from the ferroelectric memory cell with stability, resulting in a less reliable device.
DISCLOSURE OF THE INVENTION
The present invention is achieved to solve the above-mentioned problems. A ferroelectric memory is provided, by which data can be read from a ferroelectric memory cell with stability in the event of deterioration on ferroelectric forming the memory cell, the data can be positively read from the ferroelectric memory cell even if a ferroelectric capacitor has a small Cb/Cs, and the reliability of the device is thus improved.
In order to solve the above-mentioned problems, the ferroelectric memory of the present invention, which uses an electric-holding characteristic of the ferroelectric capacitor and stores digital data with the ferroelectric capacitor serving as a memory device, is provided with the ferroelectric capacitor and a selective transistor for selecting the capacitor, the ferroelectric memory further including a ferroelectric memory cell in which the drain or the source of the selective transistor is connected to

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