Image signal processing apparatus for image sensor

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Reexamination Certificate

active

06522359

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image signal processing apparatus for image sensor used for reading image data.
2. Description of the Prior Art
For an image input device such as a facsimile equipment, contact type image sensors using photo transistor sensor elements are used, for example, as disclosed in Mitsubishi Electric Corporation integrated electron device catalogue H-C0274-C, 9109 (ROD). The object of the image enlargement and reduction processes for image signal read from the image sensor is not only to magnify or reduce a manuscript but also to compensate the inconsistency of size or resolution between an input device and an output device, which is extremely important processing technique. For the image enlargement and reduction enlargement and reduction processes for image signal, a method of thinning, superposition or interpolation and so on, which is carried out after the image signal is changed to binary codes, is commonly used.
This kinds of techniques are disclosed in a laid-open Japanese patent publication No.4-315360 and a laid-open Japanese patent publication No.4-332255. It is possible to carry out enlargement and reduction processes flexibly by means of a relatively simple logic circuit. According to these processing methods, enlargement or reduction ratio can be changed programmably, which has therefore few errors. It is further possible to use relatively low frequency for a basic system clock.
FIG. 13
shows a block diagram of a conventional image signal processing apparatus for image sensor.
FIG. 14
shows a timing chart between an image input and output of an image signal processing apparatus for image sensor.
In
FIG. 13
, image sensor
1
sequentially outputs an image data SIG which the image sensor has read according to a start pulse SI and a clock pulse CLK
1
inputted from a timing generator
4
. A sample hold circuit
2
holds an image data SIG for a predetermined period according to a sample hold pulse S/H inputted from a timing generator
4
. AD converter
3
receives image data SIG
0
from the sample hold circuit
2
, and converts the image data SIG
0
from an analog signal to a digital signal according to AD conversion clock (ADC CLOCK) inputted from AD conversion clock generator
5
. A timing generator
4
generates a timing signals (SI, CLK
1
and S/H) according to a system clock &phgr; inputted from a system clock generator
6
, a start pulse SII and a control signal (PARAMETER DATA) for setting an operation mode of the image signal processing apparatus. AD conversion clock generator
5
generates ADC CLOCK according to a system clock &phgr;, a start pulse SII and a control signal (PARAMETER DATA). A system clock generator
6
generates a system clock &phgr;. A start pulse SII and control signal PARAMETER DATA are inputted from CPU or a system when necessary which is not illustrated in FIG.
13
.
An operation of the prior art is explained below.
FIG. 14
shows an example of timing in case of carrying out reduction processing. That is, a frequency division ratio of a system clock &phgr; of an image processing side takes a value of m
1
=8 and a frequency division ratio of a system clock &phgr; of an image input side take a value of m
2
=6 (see CTR
1
).
FIG. 14
also shows a timing in case that a system clock includes a frequency division value of 5 for every three times in the frequency division value of 6 (see CTR
2
).
An image processing side timing is generated by dividing the system clock supplied from the system clock generator
6
by 8. An image processing side not illustrated in
FIG. 14
takes images in synchronism with the image processing side timing (see arrow A in FIG.
14
).
In an image input side timing chart shown in bottom part of
FIG. 14
, CTR 0~2 illustrate respective output bits of a counter incorporated in the timing generator
4
. The counter is not illustrated in FIG.
14
. The counter counts the system clock and a frequency division value changes 5, 6, 6 in turn. A clock pulse CLK
1
and a sample hold pulse S/H are generated from these signals.
An image data SIG from the image sensor is outputted in synchronism with the clock pulse CLK
1
. In
FIG. 14
, image data SIG are read according to the order of a, b, c, . . . , j. The sample hold pulse S/H is a signal for clamping the image data SIG. The image data SIG becomes logical high “H” for a predetermined period where the image data SIG takes the peak value just before clock pulse CLK
1
starts to rise. A value of the image data SIG
0
is changed by the peak value of the image data SIG when sample hold pulse S/H is generated. An image data SIG
0
becomes a, b, c, . . . , j corresponding to the value of image data SIG. The image data SIG
0
is taken into the image processing side at the timing as shown by arrows in FIG.
14
.
By the way, since a frequency division value of the timing of the image processing side system clock is different from that of the image input side system clock, the image data SIG does not correspond to the data at the image processing side by one to one. Each data which are read into the image processing side is in the order of a, c, d, f, g, h (or i), j in turn. In other words, 7 image data are read out of 10 image data a, b, . . . . , j. In general, assuming that the number of picture elements and clock frequency of the picture element at the image processing side are N
1
, f
1
, respectively, and the number of picture elements and clock frequency of the picture element is N
2
, f
2
, respectively, the following relation ship can be obtained.
N
1
×
f
2
=
N
2
×
f
1
By using the circuit which makes the above operation possible, it is possible not only to simply enlarge or reduce an image but also to convert freely the picture element density of a sensor. In other words, it is possible to realize extremely flexible high density using only one kind of picture element density, such as taking out image signals of 300 dpi easily by using, for example, a sensor having 16 dots/mm.
Considering a point shown by arrow A on SIG
0
timing in
FIG. 14
, a timing for taking the image data into the image processing side overlaps to a timing where the image data SIG
0
changes its value. At the point A, since image data SIG
0
changes its step shape, data taken in are unstable and then it is impossible to take in a correct image information at the image processing side. Accordingly, periodical vertical lines appear in outputted image. Since both of the image processing side timing and the image input side timing are generated by the same system clock &phgr;, it is not possible to prevent the occurrence of above periodical vertical lines.
When an enlargement processing is carried out, there occur following problems. When the enlargement processing is carried out, frequency of clock pulse CLK
1
is set lower than that of 100% enlargement ratio.
FIG. 15
shows a relation among clock pulse CLK
1
, sample hold pulse S/H, image data SIG and SIG
0
for each 100% (same ratio) and 200% (twice) enlargement ratio, respectively.
As shown in
FIG. 15
, period of logical low “L” of clock pulse CLK
1
for 200% enlargement ratio is longer than “L” period of clock pulse CLK
1
of 100% enlargement ratio. Image data SIG is outputted as an integral waveform from image sensor
1
during “L” period of clock pulse CLK
1
. Although the peak value V of the output waveform of the image data SIG increases when “L” period of clock pulse CLK
1
is getting longer, but the peak value V saturates gradually.
In
FIG. 15
, period of sample hold point of 200% enlargement processing of image data is longer than that of 200% enlargement processing. Therefore, a relation between the level (V100%) of SIG
0
at 100% enlargement processing and the level (V200%) of SIG
0
at 200% enlargement processing is expressed as V100%<V200%, which means that levels of image data are different according to the respective enlargement ratios. Since the image data SIG is an integral waveform, sampled values V100 and V20

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