Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-13
2004-02-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06694498
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor lithography, and more specifically to addressing overlay errors that can occur in semiconductor lithography.
2. Prior Art
One of the most important requirements for semiconductor lithography is overlay, or image placement of one lithographic level relative to another. Overlay errors of one level relative to the prior level are often numerically broken down into systematic and non-systematic components; systematic components are typically: X and Y translation [zeroth order error]; and Lithographic field X and Y magnification, rotation, and skew [first order error across the wafer]
These zeroth and first-order components are chosen specifically because the errors are relatively easily correctable, and while there are repeatable higher-order effects, they are typically not easily fixable and are lumped in as “residual” errors. The correctable components are often referred to as overlay systematics, and are used to generate overlay offsets (settings) which are transferred to the aligner to achieve proper overlay.
To achieve good overlay, there are numerous approaches. For “easy” (loose overlay specification relative to aligner and process capability) levels, a fixed set of overlay offsets can be used with reasonable success. As specifications tighten, it is necessary to periodically update overlay offsets. One method of this update is to couple a database with a software data filtering means and averaging algorithm to automatically adjust these offsets. Because of either process/aligner variability or aligner shifts, an average of past offsets, no matter how well sorted, is not necessarily the optimum predictor of what a current lot needs for best overlay. In summary, the current state of the art uses feedback methods, based on population means, as a predictor for aligner settings.
The problem of optimized overlay is central to all semiconductor lithography fabrication. Existing methods for addressing this problem typically use population averaging to remove noise or slowly react to change.
SUMMARY OF THE INVENTION
An object of this invention is to improve overlay offset methods and systems for semiconductor lithography.
Another object of the present invention is to provide feed-forward methods, in semiconductor lithography procedures, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot.
These and other objectives are attained with a method and system embodying the present invention for predicting systematic overlay affects in semiconcductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that “systematic” overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.
For example: If a first lithographic level is exposed and etched with a two microradian (&mgr;rad) rotation error, this is measurable after lithography. It is reasonable to expect (and has been experimentally proven) that this rotation error persists and is measurable at the second lithograpbic level. Although ideally this systematic distortion should measure two urad at the second level, measurement errors at either level, coupled with uncorrectable lithographic distortion, make a linear correlation with non-zero intercept likely. In addition, because of overlay calculation connections, the ideal slope for the correlation would be either +1 or −1.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
REFERENCES:
patent: 4929083 (1990-05-01), Brunner
patent: 5355306 (1994-10-01), Waldo, III
patent: 5444538 (1995-08-01), Pellegrini
patent: 5468580 (1995-11-01), Tanaka
patent: 5498500 (1996-03-01), Bae
patent: 5521036 (1996-05-01), Iwamoto et al.
patent: 5561606 (1996-10-01), Ota et al.
patent: 5699282 (1997-12-01), Allen et al.
patent: 5773180 (1998-06-01), Tomimatu
patent: 5831739 (1998-11-01), Ota
patent: 5923041 (1999-07-01), Cresswell et al.
patent: 5993043 (1999-11-01), Fujii
patent: 6061606 (2000-05-01), Ross
patent: 6456953 (2002-09-01), Peruffo et al.
Conrad Edward W.
Parrish Charles J.
Whiting Charles A.
Internationl Business Machines Corporation
Lin Sun James
Scully Scott Murphy & Presser
Smith Matthew
William D. Sabo, Esq.
LandOfFree
Feed-forward lithographic overlay offset method and system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Feed-forward lithographic overlay offset method and system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Feed-forward lithographic overlay offset method and system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3285242