Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2011-01-04
2011-01-04
Patel, Nitin C (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C713S401000
Reexamination Certificate
active
07865758
ABSTRACT:
Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
REFERENCES:
patent: 5146585 (1992-09-01), Smith, III
patent: 5327468 (1994-07-01), Edblad et al.
patent: 2003/0133451 (2003-07-01), Mahalingaiah
Swaney Scott Barnett
Ward Kenneth Lundy
Webel Tobias
Weiss Ulrich
Woehrle Matthias
Gerhardt Diana R.
International Business Machines - Corporation
Patel Nitin C
Yee & Associates P.C.
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