Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-01-21
2001-12-11
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S004110, C710S120000, C370S401000
Reexamination Certificate
active
06330694
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for FAULT TOLERANT SYSTEM UTILIZING THE PERIPHERAL COMPONENTS INTERCONNECTION BUS MONITORING CARD earlier filed in the Korean Industrial Property Office on Jan. 22
ND
of 1998 and there duly assigned Ser. No. 1911/1998.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a fault detection apparatus and method utilizing a PCI (peripheral components interconnection) bus monitoring card. More specifically, the present invention is related to an apparatus and method for guaranteeing the integrity of the PCI bus by connecting a plurality of general purpose computers using a PCI bus and comparing the PCI bus signals between or among them.
2. Related Art
Typically, fault detection systems necessarily have their own central processing unit (CPU) boards or their own input/output buses. This leads to several disadvantages: an increase in design problems; increase in the time to develop new or modified systems; increased complexity of such systems; greater cost in developing and producing such systems; and increased probability of system malfunction or failure.
Exemplars of recent efforts in the art include U.S. Pat. No. 5,822,512 for Switching Control in a Fault Tolerant System issued to Goodrum et al. The aforementioned patent is different from the present invention.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus and method for detecting fault, without providing an exclusive CPU board or input/output bus to detect fault. Rather, a PCI monitoring card is appended to the general purpose computer system, and the computer systems are connected to electronic communication media.
In one aspect of the invention, a fault tolerant system utilizing a plurality of general purpose computers equipped with PCI (peripheral components interconnection) comprises: a PCI monitoring card, connected to the general purpose computer by utilizing a PCI bus, for detecting faults by comparing the PCI bus signals of one of the general purpose computers with the PCI bus signals of the other general purpose computers; and network lines connecting the PCI monitoring card of one general purpose computer with the PCI monitoring cards of the other general purpose computers.
The PCI monitoring card is connected to the CPU(Central Processing Unit) of its computer by means of a the PCI bridge. The PCI monitoring card receives the address and data bus signals from its computer, and compares them with the address and data bus signals of the other computer. When they are different from each other, interrupt signals are generated. The PCI monitoring card transmits an interrupt signal to its computer and to the other computers.
The PCI monitoring card comprises: a FIFO( First In First Out ) memory for storing the received address and data bus signals by utilizing the PCI bus; compulsive stop logic for activating a stop signal to temporarily stop the PCI transaction when the capacity of the FIFO memory is stack full; communication ports for transmitting the address and data bus signals received from the FIFO memory to the other computers, or for receiving the address and data bus signals from the other computers; and a bus comparator for comparing the address and data bus signals of its computer with those of the other computers as respectively received from the FIFO memory and communication port, and for generating an interrupt signal when the signals are different from each other.
The FIFO memory, comprised of 32-bit clocked memories, stores the 32-bit address and data bus signals received from the PCI. When the FIFO memory is full, it generates a status signal in order to temporarily stop PCI bus transactions.
Communication ports, comprised of fiber channel communication ports, receive and transmit data from and to the other computers by utilizing fiber channels.
Communication ports, comprised of fast ethernet ports, receive and transmit data from and to the other computers by utilizing fast ethernet.
The bus comparator reports the interrupt signals to its computer and to the other computers through the PCI bus. The bus comparator comprises a dual 32-bit comparator for comparing the received 32-bit address and data bus signals.
In another aspect of the invention, a fault tolerant method utilizes the PCI (peripheral components interconnection) bus monitoring card, and comprises the steps of: receiving the address and data PCI bus signals from its computer; receiving the address and data PCI bus signals from the other computers through the network; comparing the address and data PCI bus signals of its computer with those of the other computers, and, when they are identical, comparing the next signals; generating an interrupt signal when the compared signals are different; transmitting an interrupt signal to its computer; and transmitting an interrupt signal to the other computers.
REFERENCES:
patent: 5724528 (1998-03-01), Kulik et al.
patent: 5878237 (1999-03-01), Olarig
Hong Sung-Bin
Suh Dong-Wook
Bushnell , Esq. Robert E.
Ray Gopal C.
Samsung Electronics Co,. Ltd.
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