Fault tolerant operation of field programmable gate arrays

Details Fault tolerant operation of field programmable gate arrays Fault tolerant operation of field programmable gate arrays

1999-03-03

2001-07-03

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S725000, C714S733000, C714S734000

Reexamination Certificate

active

06256758

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of integrated circuit devices and, more particularly, to fault tolerant operation of field programmable gate arrays.
BACKGROUND OF THE INVENTION
A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.
The present inventors have recently developed methods of built-in self-testing the array of programmable logic blocks and the programmable routing network in FPGAs at the device, board and system levels. These methods are set out in detail in pending U.S. patent applications Ser. Nos. 08/729,117, 08/974,799 and 09/059,552. The full disclosures in these patent applications are incorporated herein by reference.
In each of these prior methods, the reprogrammability of an FPGA is exploited so that the FPGA is configured exclusively with built-in self-test (BIST) logic during off-line testing and subsequently reconfigured to its normal operating configuration. In this way, testability at every level is achieved without utilizing FPGA resources. In other words, the BIST logic simply “disappears” when the FPGA is reconfigured for its normal system function. While the use of these test methods is effective in testing the FPGAs, they are limited to off-line testing to determine the existence and location of faults within the FPGA resources.
In many high-reliability and high-availability applications, such as, space missions or telecommunication network routers, however, the FPGA hardware must work continuously and cannot be taken off-line for testing. For these systems, on-line testing must be performed concurrently with normal system operation. When faults are detected and located in the FPGA hardware of these systems, the FPGA hardware must be reconfigured to bypass the identified faulty resources. Such a process necessarily relies on spare parts or FPGA resources to replace the defective parts.
SUMMARY OF THE INVENTION
We have recognized that a need exists to extend the lifetime of a critical mission without increasing the number of available parts. For an FPGA, a part is any one of its programmable logic blocks. Since an FPGA programmable logic block has many modes of operation, it is likely that a fault would affect only some of these modes. Accordingly, the faulty logic block is still able to properly function in the modes of operation not affected by the fault. It necessarily follows that if the remaining functioning modes of operation of the partially faulty block matches the intended function for that block, the partially faulty block may continue to be utilized as if it were fault free. Advantageously, this approach to resource utilization provides for a more gradual degradation of FPGA hardware, thus extending the useful life of the system.
In accordance with the method of the present invention carried out during normal operation of the FPGA, test patterns are applied to a programmable logic block selected from the array of programmable logic blocks as a block under test. More specifically, the test patterns are varyingly applied to the underlying modules or blocks which make-up the programmable logic block under test in order to detect and locate the existence of any faults in those blocks which affect or limit the operation of the programmable logic block under test.
In accordance with an important aspect of the inventive method, each possible mode of operation of the programmable logic block under test is completely tested. To accomplish such a complete test, the programmable logic block under test is repeatedly reconfigured and exhaustive sets of test patterns sufficient to detect all possible faults in the blocks of the programmable logic block under test are applied.
Another important aspect of the inventive method, provides for the reconfiguration and further utilization of partially faulty programmable logic blocks. By reconfiguring partially faulty programmable logic blocks to avoid all operational modes affected by the detected fault, the partially faulty programmable logic blocks are allowed to continue to function in a progressively diminished, although acceptable, capacity for specific operating modes. Advantageously, this type of on-line fault tolerant reconfiguration provides for a more gradual degradation of the FPGA over prior known test methods whose primary goal is to completely bypass any faulty blocks.
The configuration, reconfiguration and control of the programmable logic block under test, on-line testing and storage of the subsequent test results are necessarily controlled by a test and reconfiguration controller and an associated storage medium. In operation, the test and reconfiguration controller accesses the FPGA through its boundary-scan ports during normal system operation (most FPGAs feature a boundary-scan mechanism). A test pattern generator provides the necessary test patterns dependent upon the configuration or mode of operation of the programmable logic block under test. The output patterns of the programmable logic block under test are compared to either known responses or output patterns produced by a reference programmable logic block receiving the same test patterns as the programmable logic block under test. The latter method is similar to the BIST techniques described in detail in the above noted pending patent applications incorporated herein by reference.
As described above, the controller further repeatedly reconfigures the programmable logic block under test for testing in all possible modes of operation. The results of the test pattern comparisons for each mode of operation of the programmable logic block under test along with usage data for the block under test are stored in the storage medium. The intended functional usage data for the block under test may be extracted at the design stage, or may be obtained utilizing a configuration decompiler which extracts the data from the configuration stream. In order to facilitate the subsequent fault tolerant reconfiguration and further operation ofthe programmable logic block under test, the results for each mode of operation are compared to the usage data for the programmable logic block under test.


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