Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-07-18
2000-02-29
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
060322659
ABSTRACT:
A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.
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Nikkei Electronics, May 9, 1983, pp. 197-202.
Akeura Nobuo
Hiramatsu Masataka
Miyazaki Yoshihiro
Oguro Hiroshi
Takaya Soichi
Beausoliel, Jr. Robert W.
Elisca Pierre E.
Hitachi , Ltd.
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