Fault tolerant cell array architecture

Details Fault tolerant cell array architecture Fault tolerant cell array architecture

2011-05-10

2011-05-10

Tseng, Cheng-Yuan (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Concurrent input/output processing and data transfer

C342S175000

Reexamination Certificate

active

07941572

ABSTRACT:
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

REFERENCES:
patent: 3868695 (1975-02-01), Kadak
patent: 4180814 (1979-12-01), Barton
patent: 4225870 (1980-09-01), Marner et al.
patent: 4337376 (1982-06-01), Gruenberg
patent: 4546428 (1985-10-01), Morton
patent: 4608569 (1986-08-01), Dickey et al.
patent: 4727503 (1988-02-01), McWhirter
patent: 4941117 (1990-07-01), Yuen
patent: 4980691 (1990-12-01), Rigg et al.
patent: 5008680 (1991-04-01), Willey et al.
patent: 5260953 (1993-11-01), Rowe
patent: 5268876 (1993-12-01), Rachlin
patent: 5573001 (1996-11-01), Petrofsky et al.
patent: 5646623 (1997-07-01), Walters et al.
patent: 5845123 (1998-12-01), Johnson et al.
patent: 6081882 (2000-06-01), Gossett
patent: 6624780 (2003-09-01), Fouts et al.
patent: 7581031 (2009-08-01), Konz et al.
patent: 7873766 (2011-01-01), Azimi et al.
patent: 2005/0228277 (2005-10-01), Barnes et al.
patent: 2008/0059761 (2008-03-01), Norman

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