Fault simulation method operable at a high speed

Details Fault simulation method operable at a high speed Fault simulation method operable at a high speed

1998-04-09

2000-03-28

Teska, Kevin J.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550005, 714 25, 714 28, G06F 9455

Patent

active

06044214&

ABSTRACT:
A fault simulation method for simulating an entire circuit represented by a gate model, comprises the steps of preparing a plurality of fault circuits represented by gate models, which are equal in number to the number of internal faults, with the internal faults assumed in the entire circuit, of dividing each of the fault circuits into a plurality of partial circuits each of which is represented by the gate model, of replacing internal faults in the partial circuits with external faults out of the partial circuits that are equivalent to the internal faults; of translating the partial circuits into translated partial circuits represented by superior models which have operation speed faster than that of the gate models, and of simultaneously simulating both of a good circuit represented by the superior model and the fault circuits represented by the superior models to determine whether or not the internal faults can be detected by comparing results of simulations. The method further may comprise a step of calculating a fault coverage for the entire circuit by repeating the above-mentioned simultaneously simulating step by the number of patterns.

REFERENCES:
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patent: 5862149 (1999-01-01), Carpenter et al.
Vinnakota et al., "Functional Test Generation for FSMs by Fault Extraction", 31st ACM/IEEE Design Automation Conference, 1994, p. 712-716.
Japanese Office Action dated Jul. 27, 1999 with partial translation.
Mao et al, "Improving Gate Level Fault Coverage by RTL Fault Grading", IEEE Proceedings of the Oct. 1996 Test Conference, pp. 150-159.
Froessl et al, "A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation", IEEE Feb. 1994 Proceedings of the European Design and Test Conference, pp. 343-348.
Joobbani, "Functional-Level Fault Simulation", Proceedings, IEEE International Conference on Circuits and Computers, 1980, pp. 1120-1124.
Japanese Office Action dated Oct. 20, 1999 with Partial Translation.

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