Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-29
2003-05-06
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S799000, C714S724000
Reexamination Certificate
active
06560738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fault propagation path estimating method and a fault propagation path estimating apparatus for accurately estimating a fault point in a combinational logic circuit, and a recording medium therefor.
2. Description of the Related Art
A fault propagation path estimating apparatus, which extracts a path through which a faulty state may propagate in a combinational logic circuit, can be used as part of a fault diagnostic system for a sequential circuit as described in JP-A-08-146093 or JP-A-10-062494. A fault may exist inside a combinational logic circuit or a faulty state may be included in an input signal pattern.
Conventional methods of estimating a fault propagation path include an inverse logical expansion method which applies a back track method disclosed in JP-A-10-154171. This is a method of extracting a fault propagation path by comparing the estimated logical state of an input signal derived with the inverse logical expansion method and the logical state inside a combinational logic circuit derived in the process with a logical state (hereinafter referred to as “expected value”) of each node derived from a previous logical simulation of a normal circuit.
In such a method, however, when the logical states of respective signal lines (lines for connecting gates which serve as components of the circuit) are estimated, the existence of multipliers or the like in the combinational logic circuit causes a significant number of decisions for the logical states of the signal lines, leading to a long time expected for calculation. To avoid this, a method is contemplated which provides faster estimation of a fault propagation path by limiting decision processing only to the signal lines relating to the fault propagation path. A conventional fault propagation path estimating apparatus for performing such processing is hereinafter described with reference to FIG.
1
and FIG.
2
.
FIG. 1
is a block diagram showing a configuration of the conventional fault propagation path estimating apparatus, and
FIG. 2
is a block diagram showing a configuration of an implication operation unit. It should be noted that the fault propagation path estimating apparatus shown in
FIG. 1
logically estimates a fault propagation path by repeating decisions and implication operations from a signal line in a known logical state in a combinational logic circuit, and does not estimate a fault propagation path by actually inputting a signal to the combinational logic circuit.
In
FIG. 1
, the conventional fault propagation path estimating apparatus comprises input device
11
such as a keyboard, data processing unit
12
for estimating a fault propagation path in a combinational logic circuit, storage device
14
including a hard disk or memory for storing information, and output device
15
such as a display or printer.
Storage device
14
comprises logic circuit configuration storing section
141
for storing the configuration of the combinational logic circuit for which a fault propagation path is to be estimated, such as types of gates which serve as components of the circuit, connections between the gates, connections between the gates and signal lines, connections between the signal lines and the like; decision state storing section
143
for storing decision levels at the estimation of the logical states of the respective signal lines with implication operations, later described; and logical state storing section
144
for storing the logical states of the respective signal lines during estimation and the expected values of the respective signal lines, respectively. The decision level represents the accumulated number of decisions (for the entire circuit) at the point of the decision of a logical state for a signal line.
Data processing unit
12
comprises initial setting section
121
for setting the logical states of input/output terminals in the combinational logic circuit in specified states at the estimation of a fault propagation path; implication operation section
123
for estimating a logical state for each signal line in the combinational logic circuit; logical contradiction determining section
124
for determining whether or not a contradiction occurs in the logical states of the signal lines estimated by implication operation section
123
; processing end determining section
125
for determining whether or not the logical states of all the signal lines have been estimated in the combinational logic circuit; X (Don't Care) state setting section
122
for setting the initial logical state of a signal line in an unestimated logical state in an X (Don't Care) state and recording this in logical state storing section
144
; back track section
126
for erasing the decided logical state of a signal line for which the logical state has already been estimated and returning the logical states of the respective signal lines to the logical states before the decisions; logical value comparing section
130
for comparing the logical states of the respective signal lines estimated in the implication operations with the expected values of the respective signal lines to extract a fault propagation path; fault output terminal connected and related line extracting section
131
for extracting any fault propagation path of the fault propagation paths extracted by logical value comparing section
130
that has a fault thereon directly affecting an output terminal and outputting associated data to output device
15
; U (Unknown) state search section
127
for checking the logical states of the inputs and outputs of the respective gates which serve as components of the combinational logic circuit to detect any signal line in a logical state Unknown (undefined); fault propagation path affecting line search section
128
for detecting any signal line relating to any fault propagation path from the signal lines in the Unknown state; and logical value decision section
129
for deciding the logical state of a signal line in the logical state Unknown connected through a gate to the signal line on the fault propagation path detected by fault propagation path affecting line search section
128
. The signal line on the fault propagation path refers to a signal line in which the estimated logical state is different from the expected value.
As shown in
FIG. 2
, implication operation section
123
comprises implication operation-capable gate search subsection
238
for detecting any gate for which the implication operation can be performed; basic implication operation subsection
241
for estimating the logical states of respective input/output signal lines of a gate connected to the input/output terminal set by initial setting section
121
, of a gate connected to the signal line decided by logical value decision section
129
, and of the gate detected by implication operation-capable gate search subsection
238
; logical contradiction detecting subsection
240
for detecting whether or not the logical state newly estimated by basic implication operation subsection
241
contradicts previously estimated the logical state; and implication operation end determining subsection
239
for determining that all the implication operations are completed when no implication operation-capable gate is detected.
The logical states of the respective signal lines are estimated by basic implication operation subsection
241
as “0,” “1,” “X” or “U.” The newly estimated logical state of the signal line is recorded in logical state storing section
144
, and the decision level at that point is recorded in decision state storing section
143
. The implication operation-capable gate refers to a gate in which the logical state of an input or output signal line in an undecided logical state may be estimated from the decided logical state (“0” or “1”) of an input or output signal line with the implication operation based on the function of the gate.
Next, the operation of the conventional fault propagation path estimating apparatus is describe
Chung Phung M.
NEC Electronics Corporation
Young & Thompson
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