Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-21
2004-03-09
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000, C714S727000, C714S025000, C714S041000
Reexamination Certificate
active
06704894
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to fault insertion as applied to electronic integrated circuits, and, more particularly to field fault insertion with respect to reprogrammable logic devices.
To ensure that a circuit board performs to specification, it is commonplace to intentionally inject faults, bugs or errors into the system to simulate a potential component failure problem during performance, and determine if system diagnostics detect the problem and respond in an appropriate manner by, for example, switching in redundant hardware to take over the functionality of the failed component.
Fault insertion usually takes the form of short-circuiting pins on computer chips that are, used on printed wiring boards (PWB) to perform certain logic functions. The problems associated with this traditional method are many. First, by today's standards, leaded pins on these chips have very small dimensions. Short-circuiting them can be time consuming, may be difficult depending upon where the PWB is located within the system and can be dangerous to the chip itself if the pin on the chip cannot sustain a short-circuit. Wires may have to be attached to the small-pitch pins for purposes of short-circuiting them. This requires rework to the PWB, is time-consuming and could potentially damage the PWB or chip itself. The problem is becoming more severe with the move toward smaller-pitch packaging such as ball grid arrays (BGA's) where the pins of the package are under the package itself and may be unreachable from the back side of the PWB. Also, space-constrained designs make gaining access to the pins difficult.
Prior art also deals with injecting non-catastrophic errors, or faults, into hardware, with the intent of detecting the error in some manner. Some of the prior art approaches are specific to particular types of hardware e.g. memory, application specific integrated circuits (ASICs), processors, hard storage disks, etc.), which is a limiting factor. Also, most of these prior art methods require special “additional” hardware or an apparatus to assist with the error injection and detection. Some prior methods may require software to “switch on” special hardware. Thus, prior art methods have limitations of various types.
New computer chips are presently available that allow a chip designer to create and change the function of the chips at the convenience of the chip designer's site location. The latest version of these computer chips is called the on-card field Reprogrammable Logic Device or RLD. The field reprogrammable feature of the RLD gives the chip designer the ability to change the function of the chip without having the chip vendor involved in the process. This results in a computer chip that can be tailored to meet a wide variety of needs in a short period of time. The on-card capability means that the chip does not have to be unsoldered from the printed wiring board (PWB), reprogrammed while off the PWB, then resoldered to the PWB. To perform the reprogramming, chip vendors have utilized an interface called boundary scan. The boundary scan interface, sometimes referred to as the JTAG (Joint Test Action Group) interface after the organization that defined it, allows for many RLDs to be connected in a chain. This yields a single path whereby all RLDs on a PWB can be reprogrammed singularly or all at once. By connecting peripheral equipment to the JTAG interface on the PWB, a chip designer can “re-personalize” the RLDs by loading in a different code set, thereby changing the function of these devices.
It is therefore an object of this invention to overcome certain of the aforesaid limitations associated with fault insertion.
It is a further object of this invention to advantageously utilize the flexibility of reprogrammable logic devices or RLDs to enhance fault insertion methodology.
SUMMARY OF THE INVENTION
The objects set forth above as well as further and other objects and advantages of the present invention are achieved by the embodiments of the invention described hereinbelow which utilize the latest computer chip technology, namely field reprogrammable logic devices (RLDs), and applies it to solving some of the drawbacks of the traditional method of short-circuiting pins for fault insertion discussed above.
The present invention involves reprogramming an on-card RLD to insert a functional fault. If reprogramming is performed in this subtle way, the circuit card on which this RLD resides will power up successfully to a point where software diagnostics can then be executed. Most well written software diagnostics will then encounter the fault and report it. Instead of faulting at the external boundaries of the device as with traditional methods of short-circuiting pins, faulting occurs with the present methodology within the boundary of the device.
This invention does not require additional “test” hardware or software to assist in the injection of the bug or fault. Furthermore, software diagnostic programs have already been written, are operational and readily available for the circuit card that contains the RLD.
For a better understanding of the present invention, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description, and its scope will be pointed out in the appended claims.
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Abraham Esaw
Cohen Jerry
DeCady Albert
Erlich Jacob N.
Lockheed Martin Corporation
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