Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2009-02-25
2011-11-01
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000, C324S512000, C702S117000, C702S118000, C702S120000
Reexamination Certificate
active
08051346
ABSTRACT:
Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.
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Chang Paul
Hamilton Thomas A.
Qian Jun
Somasundaram Senthil
Cisco Technology Inc.
Gaffin Jeffrey A
Merant Guerrier
Patterson & Sheridan LLP
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