Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
1999-04-22
2001-06-26
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S095000, C714S724000, C714S734000
Reexamination Certificate
active
06252417
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the identification of faults within electronic circuitry and more particularly to fault identification by voltage potential signature.
BACKGROUND OF THE INVENTION
To operate properly, electronic circuitry (e.g., digital logic) must be fault free. Accordingly, numerous techniques have been developed to identify circuit faults such as level sensitive scan design (LSSD) testing, quiescent current (Iddq) measurements and delay fault measurements.
During LSSD testing of a circuit, a logical voltage pattern is applied to the circuit and the resulting logical circuit outputs are observed. The resulting logical circuit outputs then are compared to the logical expected values for the circuit, and a fault is identified by a discrepancy therebetween. LSSD testing thus employs a simple binary comparison that provides no information about the internal voltage potentials of a circuit. Faults which degrade a circuit's internal voltage potentials without affecting the circuit's logical outputs (i.e., potential faults), therefore, are unidentifiable by binary testing schemes such as LSSD testing.
During an Iddq measurement, a DC voltage pattern is applied to a circuit, the power supply current supplied to the circuit is measured and the resulting power supply current is compared to an expected power supply current in order to identify faults. Similarly, during a delay fault measurement, the voltage pattern applied to a circuit's inputs is changed from one voltage pattern to another, the time required for the circuit's outputs to change states in response thereto (i.e., the circuit delay) is measured and the resulting circuit delay is compared to an expected circuit delay in order to identify faults. While both Iddq and delay fault measurements are analog in nature (e.g., measuring an analog power supply current and an analog circuit delay), neither measurement provides information about a circuit's internal voltage potentials. Additionally, as electronic circuits progress into the deep sub-micron regime, larger sub-threshold leakage currents result diminishing the usefulness of Iddq measurements. Accordingly, a need exists for an improved method and apparatus for identifying circuit faults.
SUMMARY OF THE INVENTION
To address the needs of the prior art, an inventive logic gate is provided that comprises a sensing circuit coupled to a test output (e.g., a test output of the logic gate or a test output of an integrated circuit (IC) chip employing the logic gate). As used herein, “coupled” means coupled directly or indirectly so as to operate. The sensing circuit also is coupled to an internal node of the logic gate (i.e., a node other than an output of the logic gate) and is adapted to sense a voltage on the internal node and to output a signal indicating a level of the voltage (i.e., a voltage potential signature). The sensing circuit is not used during normal operation of the logic gate and preferably comprises only a single field-effect-transistor (FET) (e.g., a p-channel metal-oxide-semiconductor FET or “PFET”) that is directly coupled to both the internal node and to the test output.
The inventive logic gate preferably comprises a pre-charge circuit for pre-charging the test output to a predetermined voltage level prior to testing (i.e., a pre-test voltage level). The pre-charge circuit may, for example, comprise an FET such as an n-channel metal-oxide-semiconductor FET or “NFET”.
An IC chip may be formed from a plurality of the inventive logic gates wherein each logic gate comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. Each sensing circuit may be coupled to the same test output (e.g., a “common” test output for the IC chip) or to a unique test output for the sensing circuit's logic gate. Each logic gate's sensing circuit thus senses a voltage present on an internal node of the logic gate and outputs a signal indicating a level of the voltage. The sensing circuits are not used during normal operation of the IC chip. The IC chip preferably comprises one or more pre-charge circuits for pre-charging the common test output or each logic gate's test output to a pre-test voltage level.
By thus providing logic gates and integrated circuits that are testable for both the presence of and the location of potential faults IC quality assurance and IC testing/troubleshooting are greatly enhanced.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.
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Adams Frederick G.
Adams Robert D.
Cooley Edmond S.
Chang Daniel D.
International Business Machines - Corporation
Schmeiser Olsen & Watts
Shkurko Eugene I.
Wamsley Patrick
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