Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-29
2002-05-28
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
06397362
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to fault diagnosis method and system for a sequential circuit and, more particularly, to a fault diagnosis method and system for localizing a faulty position in a LSI by inference.
(b) Description of the Related Art
A fault diagnosis technique of a LSI, especially for a sequential circuit, uses a fault diagnosis dictionary (hereinafter called simply “fault dictionary”) to localize the faulty position by consulting the fault dictionary for examining the actual results of the failure, or uses a scanning path in the sequential circuit through which scanning flip-flops are written (set) and the output thereof are read out.
The method using the fault dictionary requires preparation of the fault dictionary by simulating a failure, wherein a fault is installed in a simulation of a LSI, and making data files for the fault dictionary wherein a faulty position and corresponding pass/fail information of each output pin of the LSI are tabulated. When an actual failure is found, the fault dictionary is consulted at the index thereof to infer the candidate faulty position based on the results of the pass/fail information on the output pins. If a plurality of candidate faulty positions are inferred, the plurality of candidate faulty positions are numbered for priority in a descending order of probability by using the inferred faulty positions obtained for all the test input vectors.
In the method using the fault dictionary, the fault dictionary must be prepared in advance, during which fault simulations must be performed for a prolonged period of time to make the fault dictionary to a sufficient level for practical use. Accordingly, the method has the problem in that the time length for the fault simulation is extremely large and the number of data files for the fault dictionary becomes also large as the scale of integration of an LSI increases.
Further, since the fault model used in the fault simulation is generally designed for a single stacked fault (stacked or fixed to “0” or “1” at any time) neglecting a failed floating level, the model does not correctly represent an actual operation in the case of a multiple-fault such as a short-circuit failure which involves two failed paths. If the model used in the fault simulation is upgraded to cope with such a multiple-fault, the method will be impractical, because the time length required for executing the fault simulation becomes excessively large.
The method using the scanning path technique requires that a test circuit be installed in the sequential circuit for writing/reading logical values (simply referred to as “values”, hereinafter) to/from the sequential circuit through the test circuit. When a faulty position is to be inferred, the scanning flip-flops in the sequential circuit are set by using the test circuit, and the values thereof are read through the test circuit. By comparing the values thus read from the scanning flip-flops against the expected values to judge whether the fault resides in the subject combinational circuit or the failure is transferred from the preceding stage, the candidate faulty positions are excluded one by one to find the actual faulty position.
In the scanning path technique, there is a problem in that the technique cannot be applied to a LSI which has no such a scanning path for writing/reading information to/from flip-flops. In addition, in the case of a partial scanning path configuration, the circuit path disposed between the scanning flip-flops is not necessarily a combinational circuit, and thus the diagnosis for a sequential circuit must be also used. Further, if the fault dictionary is used in this diagnosis, the problems as mentioned above arise in the diagnosis.
JP-A-8-146093 proposes a fault diagnosis method for a LSI by consecutively extracting combinational circuits which are inferred to transfer a failure, and inferring the values for the inputs of the combinational circuits based on the actual outputs thereof while inferring the failed paths therein, so as to obtain the inferred input vectors of the combinational circuits.
In the method proposed by JP-A-8-146093, if a failed signal due to a faulty combinational circuit is fed back to the faulty combinational circuit itself through a plurality of other combinational circuits, incorrect values for the inputs of the faulty combinational circuit may be inferred, resulting in an incorrect inference that the failure is transferred from another correct input of the faulty combinational circuit to thereby degrade the accuracy of the inference.
In addition, the inference of the values for the inputs of the combinational circuit based on the outputs thereof requires all the inferred input vectors to be registered in an inference table, and is applied to a large number of combinational circuits extracted by the backward tracing of the LSI. Thus the inference requires a large time length for the diagnosis of the faulty position as the scale of the LSI increases.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a fault diagnosis method for a sequential circuit in a LSI by using a pass/fail information of output pins in an actual test, a netlist in the LSI including connection information, expected values of outputs of flip-flops in the LSI for each input vector of the flip-flops.
The present invention provides, in a first aspect of thereof, a fault diagnosis method for a sequential circuit including the steps of obtaining information of expected values for outputs of s each flip-flop in the LSI based on each input vector of the each flip-flop, pass/fail information for each output pin in a test, and a netlist for the LSI;
consecutively extracting, based on the netlist, combinational circuits each having a plurality of inputs each connected to an input pin or an output of any flip-flop and a plurality of outputs each connected to an output pin or input of any flip-flop, the combinational circuit including nets and logic elements other than a flip-flop, wherein the tracing starts from a failed output pin by backward tracing to an output of any first flip-flop or an input pin, and the tracing includes forward tracing from an input pin or an output of any flip-flop found by backward tracing to an output pin or an input of any flip-flop and backward tracing from an output pin or input of any flip-flop found by forward tracing to an input pin or an output of any flip-flop;
inferring a plurality of input vectors for the inputs of each combinational circuit based on an output vector of the each combinational circuit or the pass/fail information, the output vector being inferred based on the pass/fail information;
reducing the input vectors of the combinational circuit in number by simplification so as to form the output vector of preceding combinational circuit; and
inferring a faulty position in one of the combinational circuits when no correct input vector is inferred based on the output vector of the one of the combinational circuits, the correct input vector coinciding with an expected input vector of inputs of the one of the combinational circuits.
In accordance with the faulty diagnosis method of the first aspect of the present invention, by inferring the input vectors of the combinational circuit based on the output thereof and simplifying the inferred input vectors, the faulty position in a combinational circuit can be detected with a reduced time for diagnosis operation even in the case of a feed-back loop including the combinational circuit having the faulty position.
The present invention also provides, in a second aspect thereof, fault diagnosis method for a LSI including the steps of:
obtaining information of expected values for outputs of each flip-flop in the LSI based on each input vector of the each flip-flop, pass/fail information for each output pin in a test, and a netlist for the LSI;
consecutively extracting, based on the netlist, combinational circuits each having a plurality of inputs each connected to an input pin or
Foley & Lardner
NEC Corporation
Tu Christine T.
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