Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-19
2004-01-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S816000
Reexamination Certificate
active
06681360
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronic circuits and, more particularly, to a method and circuit for testing an electronic device.
BACKGROUND OF THE INVENTION
Within the meaning of the invention and in what follows, the term “electronic circuit” is to be understood in its broadest sense. Among others, it encompasses any discrete component (packaged), any assembly of such components mounted on a printed circuit type of support to form a functional unit, any unitary component implanted on a semiconductor substrate (“on chip device”) and any assembly of such components.
By definition, the terms “logic state”, or more simply “state”, designate the electrical voltage level at a node with respect to ground. By extension, these terms also designate the electrical voltage level with respect to ground of a logic signal applied to, or delivered by, a node. In binary logic, there exist two different set states denoted 1 and 0 depending on whether the node or signal voltage is respectively equal to a supply potential (generally positive) or zero. In electronic circuits, the logic is generally a positive logic, i.e. a signal is considered to be active if it is in the 1 state. In what follows, it shall be assumed that such is the case. Moreover, if a signal applied to an input is active, this input shall sometimes be referred to as being active. Likewise, the action of applying an active signal to an input shall be referred to as activating that input.
The function of digital electronic circuits is defined by the relationship between the states of some nodes of the circuit, referred to as inputs and outputs. This relationship between the state of the inputs and the state of the outputs is commonly expressed in the form of a table known as a truth table.
The invention applies to an electronic circuit having n control inputs and p data inputs, and at least one output. In general, though not always, the numbers n and p are equal. The circuit serves both to select a data input as a function of the state of the control inputs (data input multiplexing) and to store the state of the selected data inputs. The state of the last selected input is delivered by the output between two selections. At least one control input is associated with each data input in order to achieve the input data selection function.
The inputs are activated by the level of the signals applied thereto, and not by the edges (transitions from one logic state to another) of those signals. This type of circuit comprises means for imposing the state of a data input. These means are generally activated only when there is generated a control signal for the control input associated with that input. Indeed, the state of the data input at other instants is irrelevant. In other words, it is impossible to control the state of a data input without generating a control signal for the associated control input. Moreover, it is impossible to control the state of all the data inputs at any one time. Rather, it is only possible to control the state of one data input at a time. Similarly, such a type of circuit comprises means for observing the state of the output which, in general, are only activated when there is generated a control signal for a control input.
FIG. 1
shows an example of such a circuit, which is here a multiplexed flip-flop or latch
100
having two data inputs D
1
and D
2
, two control inputs LD
1
and LD
2
associated with D
1
and D
2
respectively, and an output Q. During normal operation of this circuit when only one of the control inputs LD
1
or LD
2
is active (i.e. in the 1 state) and not the other, output Q passes to the state—1 or 0—of the associated data input, respectively D
1
or D
2
. This is the selection or multiplexing function of the circuit. When the control input that was active returns to 0, the output maintains that state until a control input is again activated. This is the memory function of the circuit.
When the two control inputs are simultaneously activated, the voltage at output Q takes on an indeterminate value because there arises an internal conflict within the circuit. The output then takes on an arbitrary state 1 or 0 depending, among other things, on the state of the data inputs. However, it is impossible to determine that level beforehand. This is why the output is considered to be in an indeterminate (or “unknown”) state identified by the symbol X in the technical literature.
When none of the control inputs is active, the output Q remains in the state it was in previously. This is the memory function of the circuit.
This normal operation is summarised in the truth table of FIG.
2
. In this table, the index n−1 designates the prior state of output Q.
A classical failure is when a circuit node enters into a set state—1 or 0—irrespective of the state of the other nodes to which it is functionally connected. This results from an electrical fault in the circuit, such as a short circuit between the node and the power supply or ground due, for example, to a speck of dust having settled on a mask during the doping stage of the circuit manufacturing process. Such a fault is described as a node sticking to a given state 1 or 0.
For circuits whose inputs are activated by signal edges, it is quite simple to detect a node sticking to a given state 1 or 0. Indeed, in such a sticking state there is no transition from one logic level to another, and this is quite easily detectable. On the other hand, with circuits whose inputs are activated by a voltage level, these faults are more difficult to detect.
Digital electronic circuits are tested using test instruments which generally call upon an automatic test pattern generating program. A test pattern is a set of signals having determined states. The program simulates the most probable faults and generates a sequence of test vectors adapted to reveal these faults. These patterns are applied to the inputs of the electronic circuit under test. Faults can be detected by observing the state of the output(s). Test instruments are based on the theory that there can be one and only one input or output at a time which is stuck on state 1 or 0.
It is known to insert in the electronic circuit some circuits dedicated to the test function, such as test cells complying to IEEE std. 1149.1b-1994, which allow test patterns to be applied to the inputs and the outputs to be observed in a specific circuit operating mode, known as the test mode. A specific serial input and serial output are then necessary for implementing the test mode according to a method known as the boundary scan test.
To avoid having to implant such circuits dedicated to the test function (which on their own can account for 20% of the chip area occupied by the circuit), it is desirable to be able to detect these faults by making the circuit operate in the normal manner. Now, it will be recalled that for a circuit such as the one shown in
FIG. 1
, it is in general impossible to control the state of a data input without generating a control signal for the associated control input.
It is then easy to detect a control input which is stuck at 0. All it takes is to generate a first and then a second test pattern, with a control signal applied to that control input which is in the 1 state in the two test patterns, and a data signal on the associated data input which changes state from one pattern to the other. If the output Q does not change state in response to the change of state of the data signal, this means that the corresponding control input is stuck at 0. This test is therefore easily implemented by test instruments.
On the other hand, known test instruments are unable to detect whether a control input is stuck in the 1 state. Indeed, if this control input is activated, the output Q passes to the state of the associated data input exactly as if there were no fault. The fault is therefore not detected. Moreover, if another control input were activated, the output Q would be in the unknown state X, since the two control inputs are simultaneously in the 1 state. Now, know
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
De'cady Albert
Dooles Matthew C.
Jorgenson Lisa K.
STMicroelectronics S.A.
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