Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-03-25
2001-04-10
Fears, Terell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080, C365S230030
Reexamination Certificate
active
06215706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memories made in the form of an array of memory cells in an integrated circuit. The present invention more specifically applies to DRAMs, that is, memories requiring a periodic refresh of the data contained by the cells.
2. Discussion of the Related Art
In this type of memories, the content of a memory cell can disappear for two reasons. On the one hand, with time, the content of the cell disappears because of leaks due to the very structure of the memory cell including a transistor which, even in the off-state, leaks slightly. On the other hand, upon each reading of a memory cell, the signal is given by a sharing of charges between a bit line stray capacitance and the storage capacitance of the memory cell. By this charge sharing, the value of the voltage in the memory cell is reduced with respect to the initially contained value.
The two above effects, which result in a loss of information in the memory cells, require two types of precautions.
First, it is necessary to organize a periodic access to each of the memory cells, to compensate the charge losses in the course of time.
Then, it is necessary to restore the initial value of the memory cell upon each access by amplifying the information of the bit line. These two precautions form a so-called refresh/ restore operation.
A disadvantage induced by refresh operations is that they adversely affect the general performance of the memory by monopolizing cycles of access thereto.
Assuming, as a specific example, that a memory cell has a holding time of its content of approximately one millisecond, it is then necessary to refresh each cell every millisecond. This refreshing is performed by reading the cells. In practice, all the cells in a row are read in a same cycle, to refresh the entire row. Assuming that the memory is formed of a network of 1024×1024 cells, a refresh cycle then has to be provided every microsecond. If the access time to a cell is approximately 100 nanoseconds, 10% of the memory capacity is lost to refreshing.
A first known solution to solve this type of problem is to increase the holding time inside the memory cells. This solution is, however, difficult to implement and is linked to the memory manufacturing process. Further, it only shifts the problem by one scaling factor.
A second conventional solution is to share the memory in two alternately operating areas. For each new read or write address, the memory changes, the other memory then being available for refresh. Such an interlaced operation solution has a double drawback. First, this solution requires, for a given storage capacity, a memory which is twice as large, which increases the cost as well as the space required. Further, this solution requires a specific program, to manage the interlaced addresses.
SUMMARY OF THE INVENTION
The present invention aims at overcoming the disadvantages of known solutions by providing a novel solution that reduces the waiting delays linked to the refresh, to the reading or to the writing of DRAMs.
The present invention also aims at accelerating the data read and write accesses in the memory.
To achieve these and other objects, the present invention provides a DRAM circuit including a plurality of memory cells organized in an array, and including switches for associating with each end of each column of the array, at least two latches controlled independently from each other to store data written into or read from the considered column.
According to an embodiment of the present invention, the latches are gathered in two pairs of sets, each set being associated with a register for storing the row address of the data contained in this latch set.
According to an embodiment of the present invention, the two pairs of sets of latches are respectively associated with a first and a second pair of input/output lines adapted to being separately connected to a first and to a second input/output terminal of the memory circuit.
According to an embodiment of the present invention, the memory circuit is provided so that the access to the array for a latch set is performed simultaneously for all latches in the set.
According to an embodiment of the present invention, the memory circuit is provided so that the access to the data contained in a latch set from outside the circuit is performed individually, each latch in a same set being individually selected by a memory cell column addressing signal.
According to an embodiment of the present invention, the memory circuit includes, associated with each latch set, a comparator of the address contained in the associated address register, with an address provided by a row address bus.
According to an embodiment of the present invention, the memory circuit includes a first plurality of read amplifiers each arranged between a first respective switch and said at least two latches associated therewith, and a second plurality of read amplifiers each arranged between a second respective switch and said at least two latches associated therewith.
According to an embodiment of the present invention, the memory circuit includes a state machine adapted to successively address the different rows of the array.
According to an embodiment of the present invention, the first and second input/output terminals of the memory circuit are interconnected.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 4422160 (1983-12-01), Watanabe
Ferrant Richard
Harrand Michel
Fears Terell W.
Galanthay Theodore E.
Morris James H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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