Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1997-02-18
1998-06-16
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Differential sensing
365208, 327 51, G11C 700
Patent
active
057682020
ABSTRACT:
A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.
REFERENCES:
patent: 4907201 (1990-03-01), Minami et al.
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5646880 (1997-07-01), Yuh
J. S. Kim, et al., "A Triple Level Matallization Technique for Gigabit Scaled DRAMS", Jun. 18-20, 1996 VMIC Conference, 1995 ISMIC, 28-33, (Jun., 1996).
K. C. Lee, et al., "Low Voltage High Speed Circuit Designs for Giga-bit DRAMs", 1996 Symposium on VLSI Circuits Digest of Techical Papers, IEEE, 104-105, (1996).
Dinh Son T.
Micro)n Technology, Inc.
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