Fast scannable output latch with domino logic input

Details Fast scannable output latch with domino logic input Fast scannable output latch with domino logic input

1999-03-04

2001-08-07

Chung, Phung M. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06272654

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improved scannable fast domino output latch.
DESCRIPTION OF THE RELATED ART
FIG. 1
illustrates a conventional latch arrangement. As shown in
FIG. 1
, the conventional latches are traditionally built with transfer gates feeding cross coupled feedback inverter pairs. In the traditional approach, writing data into the latch can be quite slow due to both getting data through the transfer gate and overcoming the feedback devices. Performance can be improved by the use of larger transfer gates. Also weaker active feedback can be used to provide improved performance. Larger transfer device requires a bigger design and all of the problems that go with the bigger design. Weaker active feedback makes for a less stable storage node.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an improved scannable fast domino output latch. Other objects of the invention are to provide a scannable fast domino output latch substantially without negative effects and that overcomes disadvantages of prior art arrangements.
In brief, a scannable fast domino output latch is provided. A scannable latch circuit includes a scan logic receiving a scan data input and a scan data clock. The scannable latch circuit includes a transistor stack receiving a data input and receiving a system clock. A first inverter is connected to the transistor stack. The first inverter provides a latch output. A feedback path logic is connected across the first inverter. The feedback path logic is activated responsive to both the system clock and the scan data clock.
In accordance with features of the invention, improved performance is provided by eliminating the transfer gate and active feedback from the critical path of the scannable latch circuit. The feedback path logic is activated when both the system clock and the scan data clock are low.


REFERENCES:
patent: 5146115 (1992-09-01), Benhamida
patent: 5751727 (1998-05-01), Martens
patent: 6108805 (2000-08-01), Rajsuman
patent: 6150869 (2000-11-01), Storino et al.

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