Fast redundancy scheme for high density, high speed memories

Details Fast redundancy scheme for high density, high speed memories Fast redundancy scheme for high density, high speed memories

1999-04-15

2000-08-22

Elms, Richard

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 700

Patent

active

061082503

ABSTRACT:
A high speed process for determining whether an externally applied address points to a memory cell or a redundant memory cell in a memory is disclosed. Identification information associated with redundant memory rows and columns is stored and compared with decoded information based upon a decoded externally applied address. This comparison determines if a memory cell of a redundant memory cell is addressed.

REFERENCES:
patent: 5204836 (1993-04-01), Reed
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5659551 (1997-08-01), Huott et al.
patent: 5805789 (1998-09-01), Huott et al .
patent: 5901093 (1999-05-01), Hiltebeitel et al.
patent: 5961653 (1999-10-01), Lalter et al.

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