Fast read domino SRAM

Details Fast read domino SRAM Fast read domino SRAM

1995-09-08

1997-09-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365204, 365190, G11C 700

Patent

active

056687613

ABSTRACT:
A system and method is disclosed for increasing read performance of domino SRAMS. A conventional word-line, which drives two transistors per cell, is replaced with two separate word-lines. The first word-line drives one transistor and the second word-line drives the other transistor. The first word-line is used to write zeros into cells, while the second word line is used to both write ones into cells and to read the contents of the cells. Since the second word-line drives only one transistor during read operations, one-half of the gate load on the writeead word-line is eliminated.

REFERENCES:
patent: 4599708 (1986-07-01), Schuster
patent: 5089992 (1992-02-01), Shinohara
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5517136 (1996-05-01), Harris et al.

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