Fast evaluation of average critical area for IC layouts

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization

Reexamination Certificate

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C716S126000, C716S129000, C716S130000

Reexamination Certificate

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07962882

ABSTRACT:
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

REFERENCES:
patent: 3983479 (1976-09-01), Lee et al.
patent: 6691293 (2004-02-01), Kanazawa
patent: 6738954 (2004-05-01), Allen et al.
patent: 6751519 (2004-06-01), Satya et al.
patent: 7543255 (2009-06-01), Sinha et al.
I. Bubel, W. Maly, T. Waas, P. K. Nag, H. Hartmann, D. Schmitt-Landsiedel, and S. Griep. AFFCCA: A tool for critical area analysis with circular defects and lithography deformed layout. In IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1995.
Ulrich Lauther. An o(nlogn) algorithm for boolean mask operations. In Design Automation Conference, 1981.
G. A. Allan and A. J. Walton. Efficient extra material critical area algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(10):1480-1486, 1999.
S. Fitzpatrick, G. O'Donoghue, and G. Cheek. A comparison of critical area analysis tools. In IEEE/SEMI advanced semiconductor manufacturing conference, 1998.
G. A. Allan. A comparison of efficient dot throwing and shape shifting extra material critical area estimation. In IEEE Symposium of Defect and Fault Tolerance in VLSI Systems, 1998.
P. K. Nag and W. Maly. Hierarchical extraction of critical area for shorts in very large Ics. In IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1995.
W. A. Pleskacz, C. H. Ouyang, and W. Maly. A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(2):151-162, 1999.
Alexander R. Dalal, Paul D. Franzon, and Michael J. Lorenzetti. A layout-driven yield predictor and fault generator for VLSI. IEEE Transactions on Semiconductor Manufacturing, 7(1):77-82, 1993.
Marko Chew and Andrzej J. Strojwas. Efficient circuit re-extraction for yield simulation application. In International Conference on Computer-Aided Design, 1987.
Y. Hamamura, K. Nemoto, T. Kumazawa, and H. Iwata. Repair yielf simulation with iterative critical area analysis for different types of failure. In IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, 2002.
Way Kuo and Taeho Kim. An overview of manufacturing yield and reliability modeling for semiconductor products. preceedings of IEEE, 87(8):1329-1344, 1999.
James A. Cunningham. the use and evaluation of yielf models in integrated circuit manufacturing. IEEE Transactions on Semiconductor Manufacturing, 3(2):61-70, 1990.
W. Maly, H. Heineken, J. Khare, and P. K. Nag. Design for manufacturability in submicron domain. In International Conference on Computer-Aided Design, 1996.
Yanwen Fei and Paul Simon and Wojciech Maly. New yield models for DSM manufacturing. In International Electron Devices Meeting (IEDM), 2000.
D. M. H. Walker. Critical area analysis. In 4th International Conference on Wafer Scale Integration, 1992.
A. V. Ferris-Prabhu. Modeling the critical area in yield forecasts. IEEE Journal of Solid-State Circuits, SC-20(4):874-878, 1985.
A. V. Ferris-Prabhu. Defect size variations and their effect on the critical area of VLSI devices. IEEE Journal of Solid-State Circuits, SC-20(4):878-880, 1985.
Ed P. Huijbregts, Hua Xue, and Jochen A. G. Jess. Routing for reliable manufacturing. IEEE Transactions on Semiconductor Manufacturing, 8(2):188-194, 1995.
Venkat K. R. Chiluvuri and Israel Koren. Layout-synthesis techniques for yield enhancement. IEEE Transactions on Semiconductor Manufacturing, 8(2):178-187, 1995.
Gerard A. Allan, Anthony J. Walton, and Robert J. Holwill. An yield improvement technique for IC layout using local design rules. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(11):1355-1362, 1992.
Venkat K. R. Chiluvuri and Israel Koren. New routing and compaction strategies for yield enhancement. In IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1992.
J. Fang, J. S. K. Wong, K. Zhang, and P. Tang. A new fast constraint graph generation algorithm for VLSI layout compaction. In IEEE International Symposium on Circuits and Systems, 1991.
Udi Manber. Introduction to Algorithms A Creative Approach. Addison-Wesley Publishing Company Inc., 1989.
Restriction Requirement mailed by the USPTO on Dec. 8, 2006 in U.S. Appl. No. 10/978,946.
Applicants' Jan. 11, 2007 Response A to Restriction Requirement mailed by the USPTO on Dec. 8, 2006 in U.S. Appl. No. 10/978,946.
Divisional U.S. Appl. No. 12/032,299, filed Feb. 15, 2008 by Qing Su et al.

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