Fast data access mode in a memory device

Details Fast data access mode in a memory device Fast data access mode in a memory device

2007-06-12

2007-06-12

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000, C713S501000, C713S502000, C713S503000, C713S600000, C713S601000

Reexamination Certificate

active

10613119

ABSTRACT:
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

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