Fast column access memory

Details Fast column access memory Fast column access memory

1985-02-11

1987-03-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1300

Patent

active

046495223

ABSTRACT:
A dynamic random access memory obtains improved access time for reading data from a multiplicity of memory cells along a given selected row. This is obtained by allowing the output data line to remain active between activations of a column enable signal. An increase in data valid time at the memory output is obtained, while allowing increased latitude in memory address setup time.

REFERENCES:
"C-MOS 256-K RAM With Wideband Output Stands by on Microwatts", Electronics, E. Hamdy et al, Jun. 14, 1984, pp. 138-143.
"64K Dynamic RAM-The High Density Solution for the 80's", MIDCON/81 Conference Record, vol. 23/1/1-5, M. K. Phinney, Nov. 10-12, 1981, pp. 1-5.
"51C64 Family 65,536x Bit CHMOS Dynamic RAM", Intel Preliminary, 1983, pp. 1-15.
"A 100 ns 256K DRAM with Page-Nibble Mode", 1983 IEEE International Solid-State Circuits Conference, K. Fujishima et al, Feb. 25, 1983, pp. 228-229 and 310.
"A 100 nx 64K Dynamic RAM Using Redundancy Techniques", 1981 IEEE International Solid-State Circuits Conference, J. Brady et al, Feb. 18, 1981, pp. 84-85.
"Static Column RAM Almost Doubles Data Rates", Electronic Design, Feb. 23, 1984, pp. 259-263.
"MOS 65536-Bit Static Column Dynamic Random Access Memory", Fujitsu Preliminary, Feb. 1983, pp. 1-18.
"A 35 ns 65K Static Column DRAM", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, F. Baba et al, Oct. 1983, pp. 447-451.

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