Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-09-25
2001-11-20
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C327S148000
Reexamination Certificate
active
06320921
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of electronic circuits, and is more specifically directed to phase-locked loops as used in data communications.
As is well known in the art, the receipt of communicated digital signals in modern communication systems, whether for voice, video, or data, often requires the generation of a clock signal from the received digital signals. This process of clock generation, particularly from a data bitstream in which the logic states vary from cycle to cycle, is referred to in the art as “clock recovery” or “clock extraction”. The clock signal that is recovered from the input signal stream is conventionally used to synchronize receiver-end signal processing circuitry with the incoming signal.
In conventional systems, phase-locked loops (PLLs) are generally used to recover a clock signal from an incoming bit stream. As is fundamental in the art, PLLs typically include a phase/frequency detector that compares the incoming signal against the current state of a generated clock signal, and generates a voltage in response to the phase relationship between the two. The voltage is applied, after filtering (e.g., by charge-pumping a capacitor in a low-pass filter) and amplification as desired, to a voltage-controlled oscillator (VCO). The VCO generates the clock signal at a frequency that varies with the voltage from the phase/frequency detector, and forwards this clock signal to the processing circuitry and to the phase/frequency detector. As the frequency and phase of the clock signal approach that of the incoming bit stream, the PLL operation stabilizes at a steady state (i.e., a “locked” condition).
PLL design and functionality is relatively straightforward when the input signal is itself periodic. However, PLL synchronization with an input bitstream of varying data is somewhat more complex, as the input signal is not strictly periodic but will, of course, depend upon the actual data being communicated. For example, assuming a duty cycle of on the order of 50%, an input bitstream of all “1” states will appear as a periodic signal of the maximum frequency; conversely, an input bitstream of random (from the viewpoint of the PLL) “0” and “1” states will not be strictly periodic, but will appear as cycles of varying frequency. The clock recovery circuitry must, of course, be capable of both locking onto such an input bitstream and also maintaining a relatively steady output clock signal.
Difficulties in clock recovery from an input bitstream are exacerbated in modern communication systems, particularly those operating over fiber optic facilities at bit rates in the GHz range. In particular, the ability of clock recovery circuitry to rapidly lock onto the underlying frequency of the bitstream, maintain a steady output clock frequency, and reject noise, becomes more important with increasing data rates.
By way of further background, a conventional phase and frequency detector integrated circuit is described in Pottbäcker, et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s”,
J. Solid State Circuits
, Vol. 27, No. 12 (IEEE, Dec. 1992), pp. 1747-1751. As described therein, a capacitor is charged or discharged, in charge-pump fashion, according to the phase relationship of the input signal to the recovered clock (both its fundamental and a quadrature phase). However, in this approach, the charge and discharge pulses are dependent upon the input data pattern, and not merely its frequency; it is believed that this dependence will cause pull-out out even at a small frequency difference especially if a series of “1” level bits are received. In addition, the capacitor is charged and discharged in a discontinuous fashion according to this approach, resulting both in a relatively slow “pull-in” (or “lock-in” ) time from a large error frequency, and also in uncontrollable jitter at small error frequencies.
Another conventional clock recovery approach, referred to as a “rotational frequency detector”, is described in Wolaver,
Phase
-
Locked Loop Circuit Design
(Prentice Hall, 1991), pp. 177-183. The rotational frequency detector relies upon a comparison of the input signal to fundamental and quadrature phases of the recovered clock signal to determine which one of four possible phase relationship “quadrants” corresponds to each edge of the input signal. The direction (i.e., clockwise or counterclockwise) in which successive input signal edges travel through a repeating sequence of these four quadrants indicates whether the input frequency is greater or less than that of the recovered clock. It has been observed, however, that the rotational frequency detector, similarly as the Pottbäcker approach, charges and discharges the low-pass filter capacitor discontinuously, again resulting in long pull-in times and also jitter. Furthermore, it is apparent from the Wolaver reference that the rotational frequency detector is relatively inefficient in detecting clock slips, and also in utilizing all available rotational information; these inefficiencies are reflected in clock signal inaccuracies and also in long response times.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a frequency/phase detector in which lock-in time is minimized.
It is a further object of the present invention to provide such a frequency/phase detector which provides a high degree of lock-in accuracy in combination with small lock-in time.
It is a further object of the present invention to provide such a frequency/phase detector which is not dependent upon the incoming data states in reaching lock-in.
It is a further object of the present invention to provide a phase-locked loop circuit having such a frequency/phase detector.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into a phase-locked loop integrated circuit having a charge pump circuit for charging and discharging a capacitor in response to a frequency/phase detector circuit. The capacitor voltage is applied to an input of a voltage controlled oscillator to generate the recovered clock. The frequency/phase detector is realized as a state machine that receives logic signals corresponding to the relationship of the input signal to fundamental and quadrature phases of the output recovered clock signal. The state machine detects the rotational direction of a large error frequency and controls a charge pump to rapidly modulate the output clock frequency in response to the detected direction, until a change in rotational direction is detected. Once the change in rotational direction is detected, slower modulation of the clock frequency is effected responsive to the detected phase relationship of the input signal and the recovered clock.
REFERENCES:
patent: 5850422 (1998-12-01), Chen
patent: 6009134 (1999-12-01), Yoon
patent: 6011822 (2000-01-01), Dreyer
patent: 6127865 (2000-10-01), Jefferson
patent: 6225927 (2001-05-01), Scott et al.
Bayard Emmanuel
Brady III W. James
Moore J. Dennis
Pham Chi
Telecky , Jr. Frederick J.
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