Static information storage and retrieval – Powering
Reexamination Certificate
2000-10-24
2001-12-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S189060, C365S189090
Reexamination Certificate
active
06327212
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device comprising a non-volatile memory and a central processing unit. More particularly, the invention relates to techniques for providing a single-chip microcomputer, a data processing device, or a microprocessor which includes a flash memory and a central processing unit having a single external power supply.
Microcomputer incorporating a flash memory are known by the designations H8/538F, H8/3048 and H8/3434F, available from Hitachi Ltd.
Memory cell transistors constituting a flash memory each have a floating gate, a control gate, a source and a drain. As such, each memory cell transistor retains binary information representing a charge injection state of its floating gate. For example, electrically charging the floating gate of a memory cell transistor brings a threshold voltage of that memory cell into a high state. When the threshold voltage is raised relative to the control gate, the memory cell prevents a current from flowing. Electrically discharging the floating gate of the memory cell lowers the threshold voltage with respect to the control gate, which allows the current to flow through the memory cell. Illustratively, bringing the threshold voltage of the memory cell higher than a word line selecting voltage level of a read state is called an erasure operation (providing a logical “1” which signifies an erasure state); while bringing the threshold voltage of the memory cell lower than the word line selecting voltage level of the read state is called a programming operation (providing a logical “0” which signifies a programming state). Alternatively, the erasure state and the programming state may be defined inversely in terms of threshold voltage.
Writing or erasing data to or from memory cell transistors presupposes that their floating gates are placed in a high electric field as needed. This requires that the voltage for erasure or programming purposes be higher than the common power supply voltage, such as 3 V or 5 V. Such a high voltage is provided as an external power supply.
SUMMARY OF THE INVENTION
To obtain a high voltage externally requires that a high voltage generating circuit be mounted on the printed circuit board on which the microcomputer is assembled. To handle high voltages involves use of a specialized printed circuit board design that typically detracts from general usability.
The inventors of this invention investigated whether it was possible to use a single power supply, such as 3 V or 5 V, from which to operate a microcomputer incorporating a flash memory. The inventors' experiments involved generating a high voltage for erasure and programming by internally boosting the voltage from a single external power supply.
Some manufacturers of microcomputers, conscious of today's demand for lower power dissipation, have their devices operate on 3 V; while, manufacturers of some systems design their products to operate from a single 5 V power supply. Whether to use a 3V or a 5 V power supply is determined according to the specifications of the system to which the microcomputer in question is applied. In this respect, it is in a semiconductor manufacturers' interest to design microcomputers which are capable of operating with a relatively wide range of available power supplies, such as from 3 V to 5 V.
With the above points taken into consideration, the inventors proceeded with their studies and brought to light some problems of the related art. There are two major charge injection methods for charging flash memories: a channel injection method and a tunnel current method. The channel injection method involves letting a relatively large current flow through the channel of a given memory cell transistor to generate hot electrons near the drain, whereby the floating gate is electrically charged. The tunnel current method involves allowing a tunneling current to flow through a relatively thin tunnel oxide (insulating) film near the drain by application of an electric field of a predetermined intensity between the floating gate and the drain, whereby electric charging is accomplished. The inventors have found that the channel injection method was not suitable for internal voltage boosting because of its need for a relatively large current. With the tunnel current method, on the other hand, simply effecting internal voltage boosting was found insufficient to implement programming and erasure of an internal flash memory in a stable manner within a relatively wide range of external power supply voltages, including those for low-voltage operations.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device, such as a microcomputer, including a non-volatile memory, such as a flash memory, which can be erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages, including those for low-voltage operations.
It is another object of the present invention to provide a semiconductor integrated circuit device, such as a microcomputer, which incorporates a non-volatile memory, such as a flash memory, which is capable of being erased and programmed electrically and which offers higher usability than previously available.
Other objects, features and advantages of the present invention will become apparent from the description provided in the following specification with reference to the accompanying drawings.
In carrying out the invention and according to one aspect thereof, there is provided a semiconductor integrated circuit device, such as a microcomputer, comprising a semiconductor substrate incorporating a non-volatile memory, such as a flash memory, which is capable of being erased and programmed electrically, and a central processing unit which is capable of accessing the non-volatile memory. The semiconductor integrated circuit device operates on a single power supply voltage supplied to an external power supply terminal of the semiconductor substrate. The non-volatile memory includes: voltage clamp means which, using a reference voltage with a low dependency on a power supply voltage, clamps an output voltage to a first voltage lower in level than the single power supply voltage; boosting means for boosting the voltage output by the voltage clamp means to a positive and a negative high voltage; and a plurality of non-volatile memory cells which can be erased and programmed by use of the positive and negative high voltages output by the boosting means.
In the semiconductor integrated circuit device of the above constitution, the voltage clamp means generates a voltage that is negligibly dependent on a supply voltage. The voltage thus generated is clamped to a voltage level which, within a tolerable range of supply voltages for the semiconductor integrated circuit device, is lower than the single supply voltage externally furnished. The clamping prevents the voltages boosted by the boosting means operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage. This in turn makes it possible to erase and program the incorporated non-volatile memory in a relatively wide range of externally supplied voltages, including those for low-voltage operations. Because these features are provided by use of a single external supply voltage, the semiconductor integrated circuit device incorporating the non-voltage memory is made easier and more convenient to use than before.
The efficiency of boosting may be enhanced by changing a substrate bias voltage common to MOS transistors (metal-oxide semiconductors; MIS or metal-insulating semiconductors may be used alternatively) carrying out charge pump operations when the boosted voltage has reached a predetermined level. Illustratively, the boosting means may include: a charge pump circuit having boosting nodes for negative high voltage generation, the boosting nodes being connected to p-channel MOS transistors and capacitors so as to implement a charge p
Ishikawa Eiichi
Matsubara Kiyoshi
Saito Yasuyuki
Sato Masanao
Yada Naoki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lam David
Nelms David
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