Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-03-19
2011-12-27
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S732000, C714S726000
Reexamination Certificate
active
08086926
ABSTRACT:
There is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by compressing a plurality of signals outputted from a plurality of scan chains in which a plurality of scan flip-flops, to which signals from the semiconductor integrated circuit device are inputted, are connected in series. For each stage of the scan chains, the failure diagnostic apparatus sets a virtual space compression circuit that compresses output signals of the scan flip-flops in the stage and a virtual pin connected to the output terminal of the virtual space compression circuit, and the output signal of the virtual pin is compared with the compression signal to diagnose the semiconductor integrated circuit device for failure.
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Fujitsu Semiconductor Limited
Kerveros James C
Staas & Halsey , LLP
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