Failure detection system, failure detection method, and...

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C702S118000, C324S500000

Reexamination Certificate

active

07043384

ABSTRACT:
A failure detection system includes a wafer test information input unit which acquires pass/fail maps for wafers for a plurality of types of semiconductor devices, displaying failure chip areas based on results of electrical tests performed on chips; an analogous test information input unit which classifies the electrical tests into analogous electrical tests with regard to analogous failures among the semiconductor devices; a subarea setting unit which assigns subareas common to the types of semiconductor devices on a wafer surface; a characteristic quantity calculation unit which statistically calculates characteristic quantities based on a number of the failure chip areas included in the subareas for each analogous electrical test; and a categorization unit which obtains correlation coefficients between the characteristic quantities corresponding to the subareas, and classifies clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold.

REFERENCES:
patent: 6392434 (2002-05-01), Chiu
patent: 6694208 (2004-02-01), Sheu et al.
patent: 6775630 (2004-08-01), Behkami et al.
patent: 2003/0011376 (2003-01-01), Matsushita et al.
patent: 2003/0055592 (2003-03-01), Buckheit et al.
patent: 2004/0049722 (2004-03-01), Matsushita
patent: 2002-359266 (2002-12-01), None
Mitsutake, K. et al., “New Method of Extraction of Systematic Failure Component”, Proc. 10thInt. Symp. Semiconductor Manufacturing, pp. 247-250, (2001).
Sugimoto, M. et al., “Characterization Algorithm of Failure Distribution for LSI Yield Improvement”, Proc. 10thInt. Symp. Semiconductor Manufacturing, pp. 275-278, (2001).
Nakamae, K. et al., “Fail Pattern Classification and Analysis System of Memory Fail Bit Maps”, Proc. 4thInt. Conf. Modeling and Simulation of Microsystems, pp. 598-601, (2001).
U.S. Appl. No. 10/865,927, filed Jun. 14, 2004, to Matsushita et al.
U.S. Appl. No. 10/801,992, filed Mar. 17, 2004, to Matsushita et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Failure detection system, failure detection method, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Failure detection system, failure detection method, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Failure detection system, failure detection method, and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3635096

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.