Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-01-21
2004-09-07
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06788596
ABSTRACT:
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2002-6235 filed on Feb. 4, 2002, the entire contents of both of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a failed cell address programming circuit and a method for programming a failed cell address for repairing a failed memory cell.
2. Description of Related Art
A semiconductor memory device is usually tested after it is packaged. When a damaged or failed memory cell is found, an address (herein after referred to as a “failed cell address”) for accessing the damaged or failed memory cell is stored in an additionally provided device. It is determined whether the failed memory cell can be repaired. If the failed memory cell can be repaired, the failed cell address stored in the additionally provided device is programmed into the semiconductor memory device by applying the failed cell address to a mode setting register.
FIG. 1
is a schematic block diagram of a conventional semiconductor memory device that is disclosed in Korean Patent Application No. 2000-57067 filed in the Korean Patent Office by the same assignee as the present invention.
As shown in
FIG. 1
, the conventional semiconductor memory device includes a memory cell array
10
, a column address decoder
12
, a row address decoder
14
, a sense amplifier
16
, a write amplifier
18
, a data input buffer
20
, a data output driver
22
, a data output buffer
24
, a mode setting resistor
26
, a failed cell address control signal generating circuit
28
, a column address buffer
30
, a row address buffer
32
, a repaired cell enable control signal generating circuit
34
, a repaired cell read/write control circuit
36
, a repaired cell
38
, switches
40
,
41
, and a comparator
42
.
The operation of the conventional semiconductor memory device of
FIG. 1
described below. The memory cell array
10
has a plurality of memory cells for storing data. The data is input to and output from the memory cells in response to a plurality of word line selection signals WL
1
-WLm from the row address decoder
14
and a plurality of column selection signals Y
1
-Yn from the column address decoder
12
,.
The column address decoder
12
generates a plurality of column selection signals Y
1
-Yn (n signals) by decoding buffered address CAi, CAiB.
The row address decoder
14
generates a plurality of word line selection signals WL
1
-WLm (m signals) by decoding buffered row address RAj, RAjB.
The sense amplifier
16
amplifies data output from the memory cell array
10
or transferred from the switch
40
in response to the read enable signal CRE.
The write amplifier
18
amplifies buffered data output from the data input buffer
20
and outputs amplified data to be sent to the memory cell array
10
.
The data input buffer
20
buffers data DQ
1
-DQy and outputs the buffered data. The data output driver
22
drives the data amplified by the sense amplifier
16
. The data output buffer
24
buffers the data driven by the data output driver
22
and outputs buffered data DQ
1
-DQy.
The mode setting register
26
stores a parallel bit test control signal PBT and a failed cell address MRSk, applied externally through input pins (not shown) in response to a mode control signal MRS, and then outputs the parallel bit test control signal PBT and the failed cell address MRSk.
The failed cell address control signal generating circuit
28
generates a failed cell column address PCEi and a failed cell row address PREj in response to the failed cell address MRSk.
The column address buffer
30
buffers the column address of an externally supplied address Ak, applied from address input pins (not shown), latches the column address, and generates buffered column address CAi, CAiB.
The row address buffer
32
buffers the row address of the externally supplied address Ak, applied from the address input pins, latches the row address, and generates buffered row address RAj, RAjB.
The repaired cell enable control signal generating circuit
34
generates a repaired cell enable signal PS when the failed cell column address PCEi and the buffered column address CAi, CAiB correspond, and the failed cell row address PREj and the buffered row address RAj, RAjB correspond.
The repaired cell read/write control circuit
36
generates the repaired cell enable signal PS in response to a control command CONTi and a read command RE, or in response to a control command CONTi and a write command WE. The repaired cell enable signal PS generated by using the control command CONTi and the read command RE is used as a repaired cell read control signal CRE. The repaired cell enable signal PS generated by using the control command CONTi and the write command WE is used as a repaired cell write control signal CWE.
The repaired cell
38
latches the data. The switch
40
is turned on in response to the repaired cell read control signal CRE, thereby transferring the data stored in the repaired cell
38
.
The comparator
42
compares data output from the sense amplifier
16
in response to the parallel bit test control signal PBT and generates a comparison result signal.
The switch
44
is turned on in response to the repaired cell write control signal CWE and transfers the data output from the data input buffer
20
.
The conventional semiconductor memory device shown in
FIG. 1
is electrically tested after it is packaged. After testing, when a failed memory cell is found, a failed cell address, namely, the address of a failed memory cell, is first stored in an external device. The external device programs the failed cell address into a failed cell address control signal generating circuit in the semiconductor memory device. When the address applied through the input pins of the semiconductor memory device during normal operation of the semiconductor memory device matches to the failed cell address, data can be input into or output from a repaired cell instead of the failed memory cell.
That is, when the conventional semiconductor memory device as packaged has a failed memory cell, the address of the failed cell is first stored in the external device, and then the address of the failed cell is programmed into the semiconductor memory device from the external device during repair of the semiconductor memory device.
Accordingly, the conventional semiconductor memory device uses an expensive external device to temporarily store the failed cell address during testing and repairing the packaged semiconductor memory device. As a result, the cost of testing of the semiconductor memory device is increased.
The operation of programming the failed cell address in the conventional semiconductor memory device is described below referring to FIG.
2
.
A tester inputs the mode control signal MRS along with the parallel bit test control signal PBT into the semiconductor memory device (Step
100
). The parallel bit test control signal PBT applied to the semiconductor memory device is stored in the mode setting register
26
.
A parallel bit testing operation is performed on the semiconductor memory device in response to the parallel bit test control signal PBT (Step
110
). The parallel bit testing operation includes storing test data for testing the memory cell array
10
in the semiconductor memory device and reading the test data stored in the memory cell array
10
in parallel. The test data output from the memory cell array
10
are transmitted to the tester by a comparator
42
.
The tester determines whether the memory cell array
10
being tested is normal (Step
120
). When the test data transmitted to the tester indicates comparative consistency, the corresponding memory cell array
10
is determined to be normal, while when the test data indicates comparative inconsistency, the corresponding memory cell array
10
is determined to be abnormal or failed.
If the tester indicates that the tested memory cell array
10
is abnormal or fa
Kim Jae-Hoon
Oh Hyo-Jin
Seo Dong-Il
Harness & Dickey & Pierce P.L.C.
Phung Anh
Samsung Electronics Co,. Ltd.
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