Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2007-03-06
2007-03-06
Schillinger, Laura M. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000, C257S700000, C257S784000
Reexamination Certificate
active
10705706
ABSTRACT:
A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
REFERENCES:
patent: 3748543 (1973-07-01), Roberson
patent: 3878555 (1975-04-01), Freitag et al.
patent: 4376287 (1983-03-01), Sechi
patent: 4602271 (1986-07-01), Dougherty et al.
patent: 4688150 (1987-08-01), Peterson
patent: 4969257 (1990-11-01), Sato et al.
patent: 4975765 (1990-12-01), Ackermann et al.
patent: 5153385 (1992-10-01), Juskey
patent: 5173766 (1992-12-01), Long et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5218759 (1993-06-01), Juskey et al.
patent: 5258330 (1993-11-01), Khandros et al.
patent: 5313365 (1994-05-01), Pennisi et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5381039 (1995-01-01), Morrison
patent: 5399903 (1995-03-01), Rostoker et al.
patent: 5467252 (1995-11-01), Nomi et al.
patent: 5537738 (1996-07-01), Cathey et al.
patent: 5579207 (1996-11-01), Hayden et al.
patent: 5612256 (1997-03-01), Stansbury
patent: 5653017 (1997-08-01), Cathey et al.
patent: 5760470 (1998-06-01), Stansbury
patent: 5766053 (1998-06-01), Cathey et al.
patent: 5786232 (1998-07-01), Stansbury
patent: 5910705 (1999-06-01), Cathey et al.
patent: 5976912 (1999-11-01), Fukutomi et al.
patent: 6104135 (2000-08-01), Stansbury
patent: 6172456 (2001-01-01), Cathey et al.
patent: 6365432 (2002-04-01), Fukutomi et al.
patent: 6746897 (2004-06-01), Fukutomi et al.
patent: 0 091 072 (1983-10-01), None
patent: 0 391 790 (1990-10-01), None
patent: 0391790 (1990-10-01), None
patent: 0 091 072 (1993-10-01), None
patent: 0 582 052 (1994-02-01), None
patent: 59-043554 (1984-03-01), None
patent: 59043554 (1984-03-01), None
patent: 59-208756 (1984-11-01), None
patent: 59231825 (1984-12-01), None
patent: 60160624 (1985-08-01), None
patent: 61-177759 (1986-08-01), None
patent: 61-222151 (1986-10-01), None
patent: 61222151 (1986-10-01), None
patent: 62-23091 (1987-10-01), None
patent: 63-503261 (1988-11-01), None
patent: 64-089595 (1989-04-01), None
patent: 1289273 (1989-11-01), None
patent: 2-153542 (1990-06-01), None
patent: 2153542 (1990-06-01), None
patent: 3094430 (1991-04-01), None
patent: 3094459 (1991-04-01), None
patent: 03-178152 (1991-08-01), None
patent: 4-26545 (1992-03-01), None
patent: 4072658 (1992-03-01), None
patent: 04-180244 (1992-06-01), None
patent: 04-241445 (1992-08-01), None
patent: 04 277636 (1992-10-01), None
patent: 4277636 (1992-10-01), None
patent: 05-082667 (1993-04-01), None
patent: 5-129473 (1993-05-01), None
patent: 05-190584 (1993-07-01), None
patent: 05-226387 (1993-09-01), None
patent: 6053383 (1994-02-01), None
patent: 6-112354 (1994-04-01), None
patent: 07-058161 (1995-03-01), None
patent: WO 87/04316 (1987-06-01), None
patent: WO 90/13991 (1990-11-01), None
patent: WO 92/05582 (1992-04-01), None
patent: WO 92/21150 (1992-11-01), None
patent: WO 94/22168 (1994-09-01), None
European Patent Office Action dated Jan. 5, 2004, for EP No. 95 912 471.
European Office Action of patent application No. 02003791.7-1235 dated Apr. 4, 2005.
European Office Action of patent application No. 02003792.5-1235 dated Apr. 4, 2005.
European Office Action of patent application No. 02003794.1-1235 dated Apr. 4, 2005.
Japanese Office Action dated Jun. 14, 2005 for No. 2004-160857, and English translation.
Japanese Office Action, for Japanese Patent Application No. 2004-160856, dispatched Feb. 8, 2005, w/English translation.
Japanese Office Action, for Japanese Patent Application No. 2004-160857, dispatched Mar. 15, 2005, w/English translation.
Japanese Office Action, for Japanese Patent Application No. 2004-160858, dispatched Feb. 8, 2005, w/English translation.
Japanese Office Action, for Japanese Patent Application No. 2004-160860, dispatched Feb. 8, 2005, w/English translation.
Matsuo et al., “Smallest Flip-Chip-Like Package Chip Scale Package (CSP)”, The Second VLS Packaging Workshop of Japan 1994.
Nikkei Materials & Technology 94.4 (No. 140).
Tummala et al.; Microelectronics Packaging Handbook: Semicondcutor Packaging Second Edition Part II.
Fukutomi Naoki
Hagiwara Shinsuke
Inoue Fumio
Nomura Hiroshi
Ohhata Hirohito
Antonelli, Terry Stout and Kraus, LLP.
Hitachi Chemical Company Ltd.
Schillinger Laura M.
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