Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-02-28
1999-09-14
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438300, 438564, 438592, H01L 218238
Patent
active
059536055
ABSTRACT:
After forming an isolation layer and a well region on and in a silicon substrate, a gate oxide layer, a gate electrode of polycrystalline silicon and an oxide layer on the gate electrode are formed. Subsequently, a side wall of a nitride layer is formed. Then, the oxide layer on the gate electrode is removed. Next, selective growth of impurity doped silicon is performed at a temperature lower than or equal to 800.degree. C. to form an elevated source-drain region in a source-drain region. Also, a polycrystalline silicon layer is formed on the gate electrode. Thereafter, by performing heat treatment, the impurity is diffused from the source-drain region to the surface of the silicon substrate to form a source-drain diffusion layer. Simultaneously, conductivity is provided to the entire gate electrode by diffusing impurity from the polycrystalline silicon layer to the gate electrode.
REFERENCES:
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5168072 (1992-12-01), Moslehi
Ghandhi, VSLI Fabrication Principles, John Wiley & Sons, p. 643 1983.
Hack Jonathan
NEC Corporation
Niebling John F.
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